Lead Design Verification Job at Mirafra Technologies in San Jose

1 week ago Be among the first 25 applicants. Get AI-powered advice on this job and access more exclusive features. Responsibilities: Develop verification methodology and testbenches for digital and mixed-signal blocks. Design test plans, conduct coverage analysis, and ensure closure for parallel link and SerDes IP blocks, as well as on-chip interconnects. Basic Qualifications: BSc or MSc in Electrical Engineering, Computer Engineering, or related fields. Experience: US-based lead should have 10+ years of ASIC design verification experience. Other engineers should have 2-5 years of work or academic experience in ASIC design verification. Proven ability to handle various technical tasks independently and complete projects. Proficient in SystemVerilog and UVM testbench development for complex digital and PHY blocks, including AMS and WREAL modeling. Skilled in pre-synthesis and post-place-and-route functional verification using tools like NCSIM, VCS, ModelSim. Programming or scripting experience. Experience with version control software such as Git. Preferred Qualifications: Experience with digital designs involving multiple clock domains and clock dividers. Verification experience with SerDes IP interfaces in complex SoC environments. Knowledge of verification for PCS, PMA SerDes layers, and internal SerDes digital backends. Experience with HBM memory interface verification (PHY and controller). Familiarity with formal model equivalence checking tools and methodologies. Programming experience in Python is a plus. Seniority Level: Mid-Senior level Employment Type: Full-time Job Function: Engineering, Design, and Information Technology Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, Software Development Referrals can double your chances of interviewing at Mirafra Technologies. Get notified about new Design Specialist jobs in San Jose, CA . #J-18808-Ljbffr In Summary: US-based lead should have 10+ years of ASIC design verification experience . Other engineers should have 2-5 years of work or academic experience . Proficient in SystemVerilog and UVM testbench development for complex digital and PHY blocks, including AMS and WREAL modeling . En Español: 1 semana atrás Estar entre los primeros 25 solicitantes. Obtenga asesoramiento basado en inteligencia artificial sobre este trabajo y acceder a características más exclusivas. Responsabilidades: Desarrollar metodología de verificación y testbens para bloques digitales y de señales mixtas. Diseñar planes de prueba, realizar análisis de cobertura y asegurar el cierre de vínculos paralelos y bloques IP SerDes, así como interconexiones on-chip. Qualificaciones básicas: BSc o MSc en Ingeniería Elérica, Ingenieria Informática o campos relacionados. Experiencia: líder con sede en Estados Unidos debe tener 10+ años de experiencia en verificación del diseño ASIC. Otros ingenieros deben tener 2-5 años de trabajo o experiencia académica en la verificación de diseños ASIC Experiencia en programación en Python es una ventaja. Nivel de antigüedad: nivel medio-senior Tipo de empleo: Función de trabajo a tiempo completo: Ingeniería, Diseño y Industrias de Tecnología de la Información: Fabricación de Hardware informática, fabricación de semiconductores, Referencias para el Desarrollo de Software pueden duplicar sus posibilidades de entrevistarse en Mirafra Technologies.