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System Architect – RISC-V ASIC | Defense & Cybersecurity

System Architect – RISC-V ASIC | Defense & Cybersecurity

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Work Type: Full-Time | Onsite – Salt Lake City UT / Boise ID

Experience: 8–30 Years (ASIC design, SoC architecture, fabrication & verification)

Compensation: USD $200,000 – $300,000 annually

Job Overview

We are seeking an experienced System on Chip (SoC) Architect to lead the design and deployment of secure system solutions through RISC-V ASIC architectures for defense and critical infrastructure. This role involves technical leadership across hardware, software, and verification teams to transition existing RTL into a production-ready ASIC while ensuring performance, power, cost, and security requirements are met. The selected candidate will drive architecture definition, verification strategies, customer engagement, and roadmap planning to achieve first-pass silicon success.

Key Responsibilities

• Lead a cross-functional team (hardware, software, verification) to design, simulate, fabricate, and iterate RISC-V ASIC SoC products.
• Own microarchitecture definition, ASIC specification, and documentation including performance, I/O, power, area utilization, recurring cost, and security functionality.
• Define and oversee comprehensive verification strategy (testbench, functional, performance) to maximize probability of first-pass success.
• Act as the primary technical interface with customers, internal teams, and subcontractors to define use cases, features, and requirements.
• Guide RTL finalization, synthesis, place-and-route, timing closure, and verification activities.
• Evaluate emerging ASIC technologies and methodologies for adoption.
• Define product roadmaps, prioritize feature inclusion, and decompose into actionable design tasks.
• Identify strategic partners for development, marketing, and sustainment of products.
  
  

• Education: BS in Computer Engineering, Computer Science, Electrical Engineering, or related field.
• 8+ years of ASIC design & architecture experience.
• Proven track record in designing and fabricating ASICs.
• Strong expertise in RTL coding (Verilog/VHDL), ASIC flows, and EDA tools.
• Deep knowledge of processor architectures (RISC-V preferred).
• Hands-on experience with ASIC design methodologies (synthesis, P&R, timing closure).
• Strong leadership in cross-functional SoC/ASIC teams.
  
  

• Knowledge of applied cryptography and cybersecurity for embedded/operational systems.
• Familiarity with secure microprocessor markets and architectures.
• US Security Clearance (Active or recent within 2 years).
  
  

• Must be a US Citizen (due to project nature).
• Stable career history – no frequent job changes every 2–3 years.
• Must not be employed with Idaho Scientific (No-Poach).
• Willingness to work onsite in Salt Lake City, UT or Boise, ID.
• Flexibility for 2–3 interview rounds (technical + executive, including CEO).

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Software Development

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