ASICSoft
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Early-stage semiconductor startup developing
Edge AI Accelerator chips
for the embedded AI consumer market. With fewer than 25 employees, the company has already taped-out three chips with their current design team. As they enter their next phase of growth, they are seeking a
hands-on Sr. Design Verification Lead
to define and drive the future of their verification strategy. Role Overview As the
Sr. Design Verification Lead , you will take ownership of the company’s overall
DV architecture and methodology . You’ll work closely with internal design teams and customers to build the verification infrastructure for next-generation chips. In the first 12–18 months, you will serve as the
primary DV expert , executing hands-on verification based on the environment you architect. As the company grows, you will
recruit, mentor, and lead
a team of DV engineers, shaping the verification function for scale. Responsibilities Define, develop, and implement the
overall design verification architecture . Build
complex verification environments from the ground up
using SystemVerilog and UVM. Partner with design teams and customers to ensure verification strategies align with product requirements. Own testbench development, stimulus generation, checkers, coverage, and debug. Drive verification plans, schedules, and execution for multiple projects. Serve as the
hands-on DV lead
while building toward a leadership role in growing the DV team. Contribute to the company’s long-term success by establishing DV best practices and processes. Qualifications Education: BS with 12+ years, or MS with 10+ years, in Electrical/Computer Engineering or related field. Core Expertise: Extensive experience in
SystemVerilog . Deep knowledge of
UVM Test Bench architecture and implementation . Proven track record of
building complex verification environments from scratch . Technical Experience: Familiarity with common protocols and technologies:
I2C, SPI, PDM, Power Management, RISC-V . Preferred Experience: Previous
startup experience . Exposure to
AI accelerators
or
embedded AI . Experience with
audio-related technologies . Why Join Be a
member
of a small but growing team shaping the next generation of Edge AI hardware. Own the
end-to-end DV strategy
for an exciting product line. Transition from
hands-on contributor
to
team leader
as the company scales. Work fully remote with a
fast-moving, innovative startup
environment. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at ASICSoft by 2x Sign in to set job alerts for “Verification Specialist” roles.
Executive Assistant to VP of HR (entry level)
Mountain View, CA $160,000.00-$170,000.00 2 weeks ago San Jose, CA $181,700.00-$365,400.00 1 week ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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Edge AI Accelerator chips
for the embedded AI consumer market. With fewer than 25 employees, the company has already taped-out three chips with their current design team. As they enter their next phase of growth, they are seeking a
hands-on Sr. Design Verification Lead
to define and drive the future of their verification strategy. Role Overview As the
Sr. Design Verification Lead , you will take ownership of the company’s overall
DV architecture and methodology . You’ll work closely with internal design teams and customers to build the verification infrastructure for next-generation chips. In the first 12–18 months, you will serve as the
primary DV expert , executing hands-on verification based on the environment you architect. As the company grows, you will
recruit, mentor, and lead
a team of DV engineers, shaping the verification function for scale. Responsibilities Define, develop, and implement the
overall design verification architecture . Build
complex verification environments from the ground up
using SystemVerilog and UVM. Partner with design teams and customers to ensure verification strategies align with product requirements. Own testbench development, stimulus generation, checkers, coverage, and debug. Drive verification plans, schedules, and execution for multiple projects. Serve as the
hands-on DV lead
while building toward a leadership role in growing the DV team. Contribute to the company’s long-term success by establishing DV best practices and processes. Qualifications Education: BS with 12+ years, or MS with 10+ years, in Electrical/Computer Engineering or related field. Core Expertise: Extensive experience in
SystemVerilog . Deep knowledge of
UVM Test Bench architecture and implementation . Proven track record of
building complex verification environments from scratch . Technical Experience: Familiarity with common protocols and technologies:
I2C, SPI, PDM, Power Management, RISC-V . Preferred Experience: Previous
startup experience . Exposure to
AI accelerators
or
embedded AI . Experience with
audio-related technologies . Why Join Be a
member
of a small but growing team shaping the next generation of Edge AI hardware. Own the
end-to-end DV strategy
for an exciting product line. Transition from
hands-on contributor
to
team leader
as the company scales. Work fully remote with a
fast-moving, innovative startup
environment. Seniority level
Seniority level Mid-Senior level Employment type
Employment type Full-time Job function
Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at ASICSoft by 2x Sign in to set job alerts for “Verification Specialist” roles.
Executive Assistant to VP of HR (entry level)
Mountain View, CA $160,000.00-$170,000.00 2 weeks ago San Jose, CA $181,700.00-$365,400.00 1 week ago We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
#J-18808-Ljbffr