Insight Global
Overview
Our client is seeking an Optoelectronics Packaging Design Engineer to lead the development of advanced chip packaging solutions for laser and optoelectronic ASICs. This San Francisco-based role involves full lifecycle ownership—from design and simulation to testing and vendor coordination. The ideal candidate brings hands-on experience in semiconductor packaging, optical systems, and wafer-level processes, along with strong CAD and simulation skills. Base pay range
$125,000.00/yr - $200,000.00/yr Must-Haves
5+ years in semiconductor packaging/process development, or 2+ years with a relevant master’s degree. Proficiency in 3D CAD (e.g., SolidWorks) and simulation tools (e.g., ANSYS). Hands-on experience with automated die bonding, wire bonding, and optical alignment systems. Familiarity with materials like multi-layer ceramics, CMOS sensors, BGA packages, and organic substrates. Experience with wafer-level processes (e.g., thin film deposition, etching, bonding, dicing). Working knowledge of failure analysis tools (e.g., X-ray, SEM, microscopy). Experience with optical systems (e.g., LiDAR, cameras, microscopes). Nice-to-Haves
Degree in Materials Science, Electrical or Mechanical Engineering. Experience with automated test environments and statistical analysis for production. Background in microelectronic/photonics assembly processes. Familiarity with automotive standards like AEC-Q100. Day-to-day
Design and simulate high-performance chip packages for laser and optoelectronic ASICs. Collaborate with hardware and manufacturing teams to bring designs from concept to production. Own the full lifecycle of each chip package—from design to testing and vendor coordination. Define and execute reliability test plans. Conduct failure analysis to improve design and performance. Manage vendors for components like substrates, adhesives, PCBs, and tooling. Seniority level
Mid-Senior level Employment type
Full-time Job function
Design and Engineering Industries: Semiconductor Manufacturing
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Our client is seeking an Optoelectronics Packaging Design Engineer to lead the development of advanced chip packaging solutions for laser and optoelectronic ASICs. This San Francisco-based role involves full lifecycle ownership—from design and simulation to testing and vendor coordination. The ideal candidate brings hands-on experience in semiconductor packaging, optical systems, and wafer-level processes, along with strong CAD and simulation skills. Base pay range
$125,000.00/yr - $200,000.00/yr Must-Haves
5+ years in semiconductor packaging/process development, or 2+ years with a relevant master’s degree. Proficiency in 3D CAD (e.g., SolidWorks) and simulation tools (e.g., ANSYS). Hands-on experience with automated die bonding, wire bonding, and optical alignment systems. Familiarity with materials like multi-layer ceramics, CMOS sensors, BGA packages, and organic substrates. Experience with wafer-level processes (e.g., thin film deposition, etching, bonding, dicing). Working knowledge of failure analysis tools (e.g., X-ray, SEM, microscopy). Experience with optical systems (e.g., LiDAR, cameras, microscopes). Nice-to-Haves
Degree in Materials Science, Electrical or Mechanical Engineering. Experience with automated test environments and statistical analysis for production. Background in microelectronic/photonics assembly processes. Familiarity with automotive standards like AEC-Q100. Day-to-day
Design and simulate high-performance chip packages for laser and optoelectronic ASICs. Collaborate with hardware and manufacturing teams to bring designs from concept to production. Own the full lifecycle of each chip package—from design to testing and vendor coordination. Define and execute reliability test plans. Conduct failure analysis to improve design and performance. Manage vendors for components like substrates, adhesives, PCBs, and tooling. Seniority level
Mid-Senior level Employment type
Full-time Job function
Design and Engineering Industries: Semiconductor Manufacturing
#J-18808-Ljbffr