Video IP RTL Design Engineer Job at LanceSoft, Inc. in San Jose

Video/Display/Multimedia RTL IP Design Engineer

Location: San Jose, CA (Onsite/Hybrid)

Project Duration: 6 Months + possibility of extension

Responsibilities

• Direct experience designing RTL IP using Verilog/SystemVerilog
• Proven experience on Video domain IPs / Digital IPs
• Experience designing IP level protocols: MIPI CSI / MIPI DSI / DisplayPort / HDMI / SDI

Qualifications

• Hands‑on experience with FPGA device and Vivado toolchain
• Architecting / micro‑architecture design from functional specifications
• Verilog/SystemVerilog RTL coding for FPGA designs
• Synthesizable design flow: lint, CDC, synthesis, static timing, formal checking
• Knowledge of TCL, Perl, Python (advantage)
• SERDES architecture knowledge (plus)
• Strong communication and presentation skills
• Collaboration across teams and time zones

Seniority Level

Mid‑Senior level

Employment Type

Contract