Salt
Mask Layout Designer
Join a world-class engineering team driving innovation in RF, analog, and mixed-signal design for advanced SoC products. As a
Mask Layout Designer , you’ll collaborate closely with circuit design engineers to create, optimize, and verify custom RF and analog IP — from low-noise amplifiers and mixers to PLLs, data converters, and baseband filters — used in high-performance consumer technologies worldwide.
What you’ll do
Perform detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
Execute block-level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
Collaborate with designers on block-level floorplanning.
Conduct layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
What we’re looking for
BS degree with 7+ years of relevant industry experience.
Experience in
FinFET
and custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge.
Solid understanding of RC delay, electromigration, coupling, guard rings, DNW, PN junctions, and advanced process effects (LOD, WPE).
High proficiency with
CADENCE layout tools
and interpretation of CALIBRE DRC, ERC, LVS in FinFET technology (7nm preferred).
Excellent communication skills and ability to work with cross-functional teams.
Scripting skills in
PERL or SKILL
are a plus.
Seniority level: Mid-Senior level
Employment type: Contract
Location: San Diego, CA | Salary: $143,300.00-$247,600.00
Referrals increase your chances of interviewing at Salt by 2x.
#J-18808-Ljbffr
Mask Layout Designer , you’ll collaborate closely with circuit design engineers to create, optimize, and verify custom RF and analog IP — from low-noise amplifiers and mixers to PLLs, data converters, and baseband filters — used in high-performance consumer technologies worldwide.
What you’ll do
Perform detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
Execute block-level layout through full verification flow including extraction, DRC, LVS, and DFM checking.
Collaborate with designers on block-level floorplanning.
Conduct layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
What we’re looking for
BS degree with 7+ years of relevant industry experience.
Experience in
FinFET
and custom RF/analog layout for radio transceivers with deep sub-micron CMOS knowledge.
Solid understanding of RC delay, electromigration, coupling, guard rings, DNW, PN junctions, and advanced process effects (LOD, WPE).
High proficiency with
CADENCE layout tools
and interpretation of CALIBRE DRC, ERC, LVS in FinFET technology (7nm preferred).
Excellent communication skills and ability to work with cross-functional teams.
Scripting skills in
PERL or SKILL
are a plus.
Seniority level: Mid-Senior level
Employment type: Contract
Location: San Diego, CA | Salary: $143,300.00-$247,600.00
Referrals increase your chances of interviewing at Salt by 2x.
#J-18808-Ljbffr