Yochana
Role: FPGA RTL design and Board validation
We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal candidate will have a strong background in design debugging and a deep familiarity with Quartus tools. This role requires a detail‑oriented individual who can effectively contribute to software development projects while ensuring high quality deliverables.
Key Responsibilities
Design and develop RTL for FPGA applications, ensuring adherence to project specifications and timelines.
Conduct thorough design debugging to identify and resolve issues in the design process.
Perform FPGA validation and testing to ensure functionality and performance meet required standards.
Utilize Quartus tools for design synthesis, simulation, and implementation.
Collaborate with cross‑functional teams to integrate IP designs into larger systems.
Qualifications
7 to 15 years in FPGA RTL design, verification, and board level validation.
Experience with SV-UVM, Verilog, VHDL.
Protocol knowledge: AXI, PCIe, Ethernet.
Design and debug using Quartus tools is a must.
Board debug experience in lab; proficiency with lab equipment such as LA, CRO.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function IT Services and IT Consulting and Semiconductor Manufacturing
Referrals increase your chances of interviewing at Yochana by 2x.
Location: Mountain View, CA – Salary: $110,000 - $157,000.
#J-18808-Ljbffr
Key Responsibilities
Design and develop RTL for FPGA applications, ensuring adherence to project specifications and timelines.
Conduct thorough design debugging to identify and resolve issues in the design process.
Perform FPGA validation and testing to ensure functionality and performance meet required standards.
Utilize Quartus tools for design synthesis, simulation, and implementation.
Collaborate with cross‑functional teams to integrate IP designs into larger systems.
Qualifications
7 to 15 years in FPGA RTL design, verification, and board level validation.
Experience with SV-UVM, Verilog, VHDL.
Protocol knowledge: AXI, PCIe, Ethernet.
Design and debug using Quartus tools is a must.
Board debug experience in lab; proficiency with lab equipment such as LA, CRO.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function IT Services and IT Consulting and Semiconductor Manufacturing
Referrals increase your chances of interviewing at Yochana by 2x.
Location: Mountain View, CA – Salary: $110,000 - $157,000.
#J-18808-Ljbffr