The University of Texas at Austin
Radio Frequency (RF) Architect
Hiring Department:
Texas Institute for Electronics (TIE) –
Location:
Austin, TX –
Hours:
40 per week –
Duration:
Ongoing –
Status:
To Be Determined at Offer.
About Texas Institute for Electronics Texas Institute for Electronics (TIE) is a transformative, well‑funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.
Mission:
Advance the state of the art in 3D heterogeneous integration (3DHI), chiplet‑based architectures, and multi‑component microsystems to catalyze breakthroughs across microelectronics, artificial intelligence, quantum computing, high‑performance computing, and next‑generation healthcare devices.
Impact:
Backed by $1.4 billion in funding from DARPA, Texas initiatives, and strategic partners, TIE builds foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.
Technology:
Our 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions, operating at the intersection of defense electronics and commercial markets.
Benefits
Competitive health benefits (employee premiums covered 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
Flexible spending account options for medical and childcare expenses
Robust free training access through LinkedIn Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff ID card
Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
Purpose This role will develop advanced RF and mixed‑signal microsystems for high‑performance communication, radar, and sensing applications, including defining RF front‑end architectures, leading EM/circuit co‑simulation, overseeing RF testing, and collaborating to define design enablement requirements for next‑generation RF packaging.
Responsibilities
Architect RF and mixed‑signal microsystems operating across K‑band (18–27 GHz), Ka‑band (27–40 GHz), and W‑band (75–110 GHz) for high‑performance, low‑latency communication, radar, and sensing applications.
Define and drive RF front‑end architectures, including LNAs, PAs, mixers, phase shifters, and T/R modules, optimized for 3.0D integration and advanced packaging flows.
Collaborate with device, packaging, and digital architects to achieve co‑optimization of RF, thermal, and mechanical performance within heterogeneous multi‑die systems.
Lead EM/circuit co‑simulation and system‑level modeling using tools such as HFSS, ADS, AWR, or CST to validate and tune design performance across process corners and temperature.
Oversee RF testing, characterization, and calibration at wafer, die, and module levels—developing test plans, de‑embedding strategies, and measurement automation for K/W‑band hardware.
Engage with foundry, EDA, and metrology partners to define design enablement requirements for next‑generation RF packaging (e.g., hybrid bonding, AiP, glass/Si interposers).
Author technical documentation, reference designs, and design guidelines to accelerate ecosystem adoption of TIE’s 3.0D RF microsystems platform.
Other related functions as assigned.
Required Qualifications
M.S. in Electrical Engineering, Applied Physics, or related discipline focused on RF, microwave, or millimeter‑wave design.
At least 8 years of hands‑on experience designing, simulating, and testing RF/microwave ICs or modules (K‑band and above).
Deep expertise in S‑parameter characterization, on‑wafer measurements, vector network analysis, and de‑embedding methodologies.
Proficiency with RF simulation and design tools such as Keysight ADS, Ansys HFSS, Cadence AWR, CST Studio, or equivalent.
Strong understanding of electromagnetic effects in packaging—signal integrity, coupling, and loss across interposers and redistribution layers.
Proven track record in RF testing automation, data analysis, and test correlation between EM models and measured results.
Ability to work cross‑functionally with device, packaging, EDA, and system teams in a fast‑moving R&D environment.
Preferred: Austin, Texas location for close collaboration. Hybrid work arrangements possible with up to 30–50 % travel.
Relevant education and experience may be substituted as appropriate.
Preferred Qualifications
Ph.D. in Electrical Engineering, Applied Physics, or related discipline focused on RF, microwave, or millimeter‑wave design.
More than 8 years of hands‑on experience designing, simulating, and testing RF/microwave ICs or modules (K‑band and above).
Experience developing Antenna‑in‑Package (AiP), RFIC/SiP, or 3D‑stacked RF front‑end modules for advanced communications or sensing.
Familiarity with 3DHI design flows and RF/mixed‑signal co‑simulation using advanced EDA environments (Cadence, Synopsys, Siemens, Ansys).
Hands‑on experience with wafer‑level probing, cryogenic testing, or thermal‑vacuum characterization for high‑frequency systems.
Knowledge of GaAs, GaN, SiGe, or CMOS RF processes and packaging constraints for high‑frequency operation.
Publication or patent record in millimeter‑wave circuits, antennas, or RF packaging.
Strong technical writing and presentation skills for industry and defense‑sector collaborations.
Salary:
TIE pays industry‑competitive salaries.
Working Conditions
May work around chemical fumes.
May work around standard office conditions.
May work around chemicals.
May work around electrical and mechanical hazards.
Repetitive use of a keyboard at a workstation.
Use of manual dexterity (e.g., using a mouse).
Work Shift
Monday–Friday: 8 a.m. to 5 p.m., or flexible between 7 a.m. and 6 p.m.
Hybrid work arrangements possible, with up to 30–50 % travel.
Required Materials
Resume/CV
3 work references with contact information (at least one supervisor reference)
Letter of interest (optional)
Equal Opportunity Employer The University of Texas at Austin, as an equal opportunity/affirmative action employer, complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs and activities, and admissions.
Employment Eligibility Verification Selected candidates must complete the federal Employment Eligibility Verification I‑9 form and present acceptable and original documents to prove identity and authorization to work in the United States no later than the third day of employment. Failure to comply will result in loss of employment.
E‑Verify The University of Texas at Austin uses E‑Verify to check the work authorization of all new hires effective May 2015. The university’s company ID number for E‑Verify is 854197.
Pay Transparency The University of Texas at Austin will not discriminate against employees or applicants for inquiries about pay.
Retirement Plan Eligibility Retirement plan: Teacher Retirement System of Texas (TRS) for positions ≥ 20 hours per week and ≥ 135 days in length; Optional Retirement Program (ORP) available for positions ≥ 40 hours per week and ≥ 135 days in length.
Background Checks A criminal history background check will be required for finalists under consideration.
Compliance Employees may be required to report violations of law under Title IX and the Clery Act. The Clery Act requires notification of the Annual Security and Fire Safety report.
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Texas Institute for Electronics (TIE) –
Location:
Austin, TX –
Hours:
40 per week –
Duration:
Ongoing –
Status:
To Be Determined at Offer.
About Texas Institute for Electronics Texas Institute for Electronics (TIE) is a transformative, well‑funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.
Mission:
Advance the state of the art in 3D heterogeneous integration (3DHI), chiplet‑based architectures, and multi‑component microsystems to catalyze breakthroughs across microelectronics, artificial intelligence, quantum computing, high‑performance computing, and next‑generation healthcare devices.
Impact:
Backed by $1.4 billion in funding from DARPA, Texas initiatives, and strategic partners, TIE builds foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.
Technology:
Our 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions, operating at the intersection of defense electronics and commercial markets.
Benefits
Competitive health benefits (employee premiums covered 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
Flexible spending account options for medical and childcare expenses
Robust free training access through LinkedIn Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff ID card
Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
Purpose This role will develop advanced RF and mixed‑signal microsystems for high‑performance communication, radar, and sensing applications, including defining RF front‑end architectures, leading EM/circuit co‑simulation, overseeing RF testing, and collaborating to define design enablement requirements for next‑generation RF packaging.
Responsibilities
Architect RF and mixed‑signal microsystems operating across K‑band (18–27 GHz), Ka‑band (27–40 GHz), and W‑band (75–110 GHz) for high‑performance, low‑latency communication, radar, and sensing applications.
Define and drive RF front‑end architectures, including LNAs, PAs, mixers, phase shifters, and T/R modules, optimized for 3.0D integration and advanced packaging flows.
Collaborate with device, packaging, and digital architects to achieve co‑optimization of RF, thermal, and mechanical performance within heterogeneous multi‑die systems.
Lead EM/circuit co‑simulation and system‑level modeling using tools such as HFSS, ADS, AWR, or CST to validate and tune design performance across process corners and temperature.
Oversee RF testing, characterization, and calibration at wafer, die, and module levels—developing test plans, de‑embedding strategies, and measurement automation for K/W‑band hardware.
Engage with foundry, EDA, and metrology partners to define design enablement requirements for next‑generation RF packaging (e.g., hybrid bonding, AiP, glass/Si interposers).
Author technical documentation, reference designs, and design guidelines to accelerate ecosystem adoption of TIE’s 3.0D RF microsystems platform.
Other related functions as assigned.
Required Qualifications
M.S. in Electrical Engineering, Applied Physics, or related discipline focused on RF, microwave, or millimeter‑wave design.
At least 8 years of hands‑on experience designing, simulating, and testing RF/microwave ICs or modules (K‑band and above).
Deep expertise in S‑parameter characterization, on‑wafer measurements, vector network analysis, and de‑embedding methodologies.
Proficiency with RF simulation and design tools such as Keysight ADS, Ansys HFSS, Cadence AWR, CST Studio, or equivalent.
Strong understanding of electromagnetic effects in packaging—signal integrity, coupling, and loss across interposers and redistribution layers.
Proven track record in RF testing automation, data analysis, and test correlation between EM models and measured results.
Ability to work cross‑functionally with device, packaging, EDA, and system teams in a fast‑moving R&D environment.
Preferred: Austin, Texas location for close collaboration. Hybrid work arrangements possible with up to 30–50 % travel.
Relevant education and experience may be substituted as appropriate.
Preferred Qualifications
Ph.D. in Electrical Engineering, Applied Physics, or related discipline focused on RF, microwave, or millimeter‑wave design.
More than 8 years of hands‑on experience designing, simulating, and testing RF/microwave ICs or modules (K‑band and above).
Experience developing Antenna‑in‑Package (AiP), RFIC/SiP, or 3D‑stacked RF front‑end modules for advanced communications or sensing.
Familiarity with 3DHI design flows and RF/mixed‑signal co‑simulation using advanced EDA environments (Cadence, Synopsys, Siemens, Ansys).
Hands‑on experience with wafer‑level probing, cryogenic testing, or thermal‑vacuum characterization for high‑frequency systems.
Knowledge of GaAs, GaN, SiGe, or CMOS RF processes and packaging constraints for high‑frequency operation.
Publication or patent record in millimeter‑wave circuits, antennas, or RF packaging.
Strong technical writing and presentation skills for industry and defense‑sector collaborations.
Salary:
TIE pays industry‑competitive salaries.
Working Conditions
May work around chemical fumes.
May work around standard office conditions.
May work around chemicals.
May work around electrical and mechanical hazards.
Repetitive use of a keyboard at a workstation.
Use of manual dexterity (e.g., using a mouse).
Work Shift
Monday–Friday: 8 a.m. to 5 p.m., or flexible between 7 a.m. and 6 p.m.
Hybrid work arrangements possible, with up to 30–50 % travel.
Required Materials
Resume/CV
3 work references with contact information (at least one supervisor reference)
Letter of interest (optional)
Equal Opportunity Employer The University of Texas at Austin, as an equal opportunity/affirmative action employer, complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs and activities, and admissions.
Employment Eligibility Verification Selected candidates must complete the federal Employment Eligibility Verification I‑9 form and present acceptable and original documents to prove identity and authorization to work in the United States no later than the third day of employment. Failure to comply will result in loss of employment.
E‑Verify The University of Texas at Austin uses E‑Verify to check the work authorization of all new hires effective May 2015. The university’s company ID number for E‑Verify is 854197.
Pay Transparency The University of Texas at Austin will not discriminate against employees or applicants for inquiries about pay.
Retirement Plan Eligibility Retirement plan: Teacher Retirement System of Texas (TRS) for positions ≥ 20 hours per week and ≥ 135 days in length; Optional Retirement Program (ORP) available for positions ≥ 40 hours per week and ≥ 135 days in length.
Background Checks A criminal history background check will be required for finalists under consideration.
Compliance Employees may be required to report violations of law under Title IX and the Clery Act. The Clery Act requires notification of the Annual Security and Fire Safety report.
#J-18808-Ljbffr