Senior ASIC RTL Designer - Peripheral IP Lead

A leading tech company is seeking a Senior Designer in Hardware Engineering. The role involves designing peripheral IP's, mentoring junior team members, and engaging with external teams. A minimum of 12 years in ASIC IP cores design and a Bachelor's degree in Electrical Engineering are mandatory. This position is based in San Diego, California and demands strong problem-solving skills and independence. #J-18808-Ljbffr