Broadcom
Job Description
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High Speed SerDes DSP RTL Designer
role at
Broadcom .
MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
Experience in synthesis, CDC, static timing analysis.
Exposure to SDF annotated simulations with good understanding of parasitic delays.
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
Strong analytical thinking and problem-solving skills with excellent attention to details.
Must be organized, self-motivated and able to work effectively across internal and end customers teams.
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications
Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful.
Compensation And Benefits The annual base salary range for this position is $120,000 - $192,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays, paid sick leave and vacation time
Compliance with paid family leave and other leaves of absence
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High Speed SerDes DSP RTL Designer
role at
Broadcom .
MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design.
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration.
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint.
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
Experience in synthesis, CDC, static timing analysis.
Exposure to SDF annotated simulations with good understanding of parasitic delays.
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
Strong analytical thinking and problem-solving skills with excellent attention to details.
Must be organized, self-motivated and able to work effectively across internal and end customers teams.
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications
Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful.
Compensation And Benefits The annual base salary range for this position is $120,000 - $192,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays, paid sick leave and vacation time
Compliance with paid family leave and other leaves of absence
#J-18808-Ljbffr