Senior High-Speed SerDes DSP RTL Designer (Equity)

A leading semiconductor company is looking for a High Speed SerDes DSP RTL Designer in San Jose, CA. The role requires expertise in high speed ADC based SerDes RTL design and proficiency in Verilog-HDL/System Verilog coding. Candidates should have a strong background in design for test, as well as experience in high-speed serial interconnect architectures. The position offers an annual salary between $120,000 and $192,000, and includes a comprehensive benefits package. #J-18808-Ljbffr