Broadcom
Job Title
High Speed SerDes DSP RTL Designer
Location Sunnyvale, CA
Senior level Mid-Senior level
Employment type Full-time
Job function Engineering and Information Technology
Industries Semiconductor Manufacturing
Qualifications
MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high‑speed ADC based SerDes RTL design.
Proficient with Verilog‑HDL/System Verilog coding for PAM4 DSP based SerDes, including equalization, adaptation and high‑speed ADC calibration.
Experienced with front‑end tools such as NCVerilog, NCSIM, Simvision, and lint.
Exposure to Design for Test, understanding of scan concepts and writing DFT‑friendly RTL.
Deep understanding of high‑speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade‑offs to drive performance, power and cost metrics over the project lifetime.
Experience in synthesis, Clock‑Domain‑Crossing, static timing analysis.
Knowledge of SDF‑annotated simulations and parasitic delay analysis.
Experience in design management with detailed knowledge of development methodologies, design flows, EDA integration, foundry PDKs and associated collateral.
Strong analytical thinking and problem‑solving skills with excellent attention to detail.
Organized, self‑motivated and able to work effectively across internal and end‑customer teams.
Excellent knowledge/experience with TSMC 7nm‑2nm process, including power consumption, area estimation, layout effort for digital and analog blocks, and technology limitations.
Highly Desired Qualifications
Understanding of micro‑architecture with standard peripherals (AMBA bus, I2C/SPI/UART).
Deep knowledge of Signal Integrity and Power Integrity modeling for high‑speed designs.
Experience with Verilog AMS simulation and behavioral analog circuit modeling.
Compensation And Benefits
The annual base salary range for this position is $120,000 – $192,000.
This position is eligible for a discretionary annual bonus and equity awards.
Broadcom offers a comprehensive benefits package: medical, dental and vision plans, 401(K) with company match, Employee Stock Purchase Program, Employee Assistance Program, paid holidays, paid sick leave, vacation time and Paid Family Leave.
Equal Employment Opportunity Broadcom is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, age, disability, or any other protected status.
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Location Sunnyvale, CA
Senior level Mid-Senior level
Employment type Full-time
Job function Engineering and Information Technology
Industries Semiconductor Manufacturing
Qualifications
MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high‑speed ADC based SerDes RTL design.
Proficient with Verilog‑HDL/System Verilog coding for PAM4 DSP based SerDes, including equalization, adaptation and high‑speed ADC calibration.
Experienced with front‑end tools such as NCVerilog, NCSIM, Simvision, and lint.
Exposure to Design for Test, understanding of scan concepts and writing DFT‑friendly RTL.
Deep understanding of high‑speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade‑offs to drive performance, power and cost metrics over the project lifetime.
Experience in synthesis, Clock‑Domain‑Crossing, static timing analysis.
Knowledge of SDF‑annotated simulations and parasitic delay analysis.
Experience in design management with detailed knowledge of development methodologies, design flows, EDA integration, foundry PDKs and associated collateral.
Strong analytical thinking and problem‑solving skills with excellent attention to detail.
Organized, self‑motivated and able to work effectively across internal and end‑customer teams.
Excellent knowledge/experience with TSMC 7nm‑2nm process, including power consumption, area estimation, layout effort for digital and analog blocks, and technology limitations.
Highly Desired Qualifications
Understanding of micro‑architecture with standard peripherals (AMBA bus, I2C/SPI/UART).
Deep knowledge of Signal Integrity and Power Integrity modeling for high‑speed designs.
Experience with Verilog AMS simulation and behavioral analog circuit modeling.
Compensation And Benefits
The annual base salary range for this position is $120,000 – $192,000.
This position is eligible for a discretionary annual bonus and equity awards.
Broadcom offers a comprehensive benefits package: medical, dental and vision plans, 401(K) with company match, Employee Stock Purchase Program, Employee Assistance Program, paid holidays, paid sick leave, vacation time and Paid Family Leave.
Equal Employment Opportunity Broadcom is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, age, disability, or any other protected status.
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