NanoHelp
HBM Design Architect – Micron Technology, Richardson, TX (USA)
NanoHelp, Richardson, Texas, United States, 75080
Job Overview
Micron Technology seeks a highly skilled HBM Design Architect to lead the design, architecture, and integration of advanced DRAM technologies. This role focuses on nanometer‑scale DRAM array architectures, high‑speed signaling, and 2.5D/3D packaging innovations, enabling next‑generation AI, HPC, and data‑intensive systems. Key Responsibilities
Lead architecture pathfinding and feasibility analysis for new HBM generations. Collaborate with customers to refine specifications and future designs. Debug pre‑ and post‑silicon HBM issues and identify root causes. Innovate in nanotechnology‑driven DRAM arrays, signal integrity, and thermal modeling. Work with JEDEC standards, CAD, verification, and system engineering teams. Mentor engineers in advanced DRAM and packaging techniques. Required Qualifications
BSEE or higher in nanotechnology, electrical engineering, or semiconductor engineering. 10+ years in engineering/design with strong background in nanometer CMOS, DRAM architecture, and 3D integration. Expertise in memory array design. Expertise in high‑speed clocking/interfaces. Expertise in 2.5D/3D packaging (TSV, hybrid bonding, interposers). Strong understanding of semiconductor device physics. Familiarity with DRAM bring‑up, JEDEC standards, and modeling tools (FastSpice, Hspice). Benefits
Comprehensive medical, dental, and vision coverage. Paid time off and family leave. Income protection and holidays. Opportunities for professional growth in nanotechnology and semiconductor design. This job post is for informational purposes only. Please refer to Micron Technology’s official careers page for the most accurate and updated application details.
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Micron Technology seeks a highly skilled HBM Design Architect to lead the design, architecture, and integration of advanced DRAM technologies. This role focuses on nanometer‑scale DRAM array architectures, high‑speed signaling, and 2.5D/3D packaging innovations, enabling next‑generation AI, HPC, and data‑intensive systems. Key Responsibilities
Lead architecture pathfinding and feasibility analysis for new HBM generations. Collaborate with customers to refine specifications and future designs. Debug pre‑ and post‑silicon HBM issues and identify root causes. Innovate in nanotechnology‑driven DRAM arrays, signal integrity, and thermal modeling. Work with JEDEC standards, CAD, verification, and system engineering teams. Mentor engineers in advanced DRAM and packaging techniques. Required Qualifications
BSEE or higher in nanotechnology, electrical engineering, or semiconductor engineering. 10+ years in engineering/design with strong background in nanometer CMOS, DRAM architecture, and 3D integration. Expertise in memory array design. Expertise in high‑speed clocking/interfaces. Expertise in 2.5D/3D packaging (TSV, hybrid bonding, interposers). Strong understanding of semiconductor device physics. Familiarity with DRAM bring‑up, JEDEC standards, and modeling tools (FastSpice, Hspice). Benefits
Comprehensive medical, dental, and vision coverage. Paid time off and family leave. Income protection and holidays. Opportunities for professional growth in nanotechnology and semiconductor design. This job post is for informational purposes only. Please refer to Micron Technology’s official careers page for the most accurate and updated application details.
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