MediaTek
CPO High speed I/O and photonics design architect
MediaTek, San Jose, California, United States, 95199
CPO High Speed I/O and Photonics Design Architect
Location: Sunnyvale, CA
Base Pay Range $190,000.00/yr - $270,000.00/yr
Job Description
Define CPO product specifications and strategy with the design team to achieve low power, high density, low cost, and high reliability CPO solutions.
Design, simulate, budget, and analyze CPO systems at both optical and electrical levels.
Optimize signal integrity, power efficiency, and thermal management in co-packaged optics.
Requirements
Master’s or PhD in Mechanical Engineering, Electrical Engineering, Materials Science, or related field.
Experience in developing and deploying silicon photonics solutions to the market.
Experience in developing photonics, including link budget analysis.
Over 5 years of experience in semiconductor technology development roles.
Over 5 years of experience collaborating with manufacturing partners, including suppliers, OSATs, and foundries.
In-depth knowledge of various packaging architectures, as well as EIC and PIC design architectures.
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Base Pay Range $190,000.00/yr - $270,000.00/yr
Job Description
Define CPO product specifications and strategy with the design team to achieve low power, high density, low cost, and high reliability CPO solutions.
Design, simulate, budget, and analyze CPO systems at both optical and electrical levels.
Optimize signal integrity, power efficiency, and thermal management in co-packaged optics.
Requirements
Master’s or PhD in Mechanical Engineering, Electrical Engineering, Materials Science, or related field.
Experience in developing and deploying silicon photonics solutions to the market.
Experience in developing photonics, including link budget analysis.
Over 5 years of experience in semiconductor technology development roles.
Over 5 years of experience collaborating with manufacturing partners, including suppliers, OSATs, and foundries.
In-depth knowledge of various packaging architectures, as well as EIC and PIC design architectures.
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