Cadence
Lead Analog IC Designer – Cadence
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
- Design and develop analog/mixed‑signal IC circuit blocks from initial concept and specifications through final verification of conformance to customer specifications.
Qualifications
- Minimum of 3 years of experience in CMOS SerDes or high‑speed I/O IC design and development.
- Working knowledge of common SerDes standards and their electrical requirements.
- Proficient design experience in the following SerDes circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, PLL, High‑Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators.
- Excellent problem‑solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment.
- Proficiency using CAD tools for circuit simulation, layout, and physical verification.
- Cadence tool experience, lab test experience, and design experience at >112 Gbps and in <7 nm technologies are a plus.
- MS or PhD in EE.
Benefits and Compensation
- Annual salary range for California: $114,800 to $213,200. Eligible for incentive compensation: bonus, equity, and benefits.
- Paid vacation and paid holidays.
- 401(k) plan with employer match.
- Employee stock purchase plan.
- Variety of medical, dental, and vision plan options.
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