Senior SoC Clocking Architect - Lead High-Speed Design

A Silicon Valley-based hardware startup is seeking a highly experienced Clock Designer – Design Lead to drive high-speed clock distribution networks for advanced SoC designs. The role requires 15+ years of experience, a degree in Electrical Engineering, and expertise in clock timing analysis. This is an opportunity to influence AI infrastructure technology directly. The position offers a competitive salary ranging from $210,000 to $270,000 per year, commensurate with experience. #J-18808-Ljbffr