Eximietas Design
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Location: San Jose, CA (other locations can be discussed)
Experience: 10–20 Years
About the Role Eximietas Design is seeking an Analog Layout Design Lead to drive the physical implementation of high‑performance analog and mixed‑signal IP, with strong emphasis on High‑Speed SerDes PHYs (28G/56G/112G+) in advanced FinFET nodes (7nm, 5nm, and below).
This role is ideal for a hands‑on technical leader who has owned mission‑critical analog blocks, defined layout methodology, and consistently delivered first‑pass clean layouts with minimal ECOs. You will partner closely with circuit design, PD, and verification teams while mentoring layout engineers and influencing layout strategy across projects.
Key Responsibilities
Lead and own analog / mixed‑signal layout architecture for complex IP and SerDes macros.
Execute and review layouts for TX/RX, clock paths, PLL/DLL/CDR, IOs, regulators, bias circuits, and analog datapaths.
Define and enforce layout methodology including:
Precision matching, symmetry, shielding, and isolation
Parasitic optimization and noise mitigation
Power grid design, routing guides, density strategies, and metal fill solutions
Drive floorplanning and hierarchical layout strategies to optimize analog performance and scalability.
Ensure clean signoff across DRC, LVS, ERC, density, extraction, EM/IR, and reliability flows.
Collaborate with PD teams on macro integration and full‑chip assembly.
Develop or enhance PCell libraries and SKILL‑based automation to improve layout productivity and consistency.
Mentor and technically guide junior and mid‑level layout engineers across global teams.
Support silicon debug and correlation, identifying layout‑driven performance issues.
Required Skills & Experience
10–20 years of hands‑on experience in custom analog / mixed‑signal IC layout.
Proven leadership owning high‑impact analog layouts from concept through tape‑out.
Deep expertise in High‑Speed SerDes layout (28G/56G/112G+ preferred).
Strong experience across advanced process nodes (FinFET 7nm/5nm and below).
Mastery of:
Precision matching and device placement
High‑current and clock‑sensitive structures
Substrate noise, latch‑up, ESD, and reliability considerations
Extensive experience with Cadence Virtuoso, Calibre / Synopsys verification flows, and extraction tools.
Proficiency in SKILL scripting, PCell development, and layout automation.
Track record of delivering first‑pass clean layouts with disciplined scheduling.
Strong communication, problem‑solving, and cross‑functional collaboration skills.
Nice to Have
Experience defining organization‑wide layout methodology or training programs.
Prior ownership of PLL, clocking IP, or SerDes clock paths.
Exposure to post‑silicon validation and layout‑related debug.
Experience working with distributed or offshore layout teams.
Familiarity with PCIe, Ethernet, CXL, or similar high‑speed protocols.
Why Join Eximietas?
Work on next‑generation SerDes and analog IP in leading‑edge nodes.
Take on a technical leadership role with high ownership and visibility.
Influence layout methodology and best practices across projects.
Collaborate with top‑tier semiconductor teams in California and Texas.
Apply or refer at
mohini.tyagi@eximietas.design
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Engineering, Research, and Consulting
Industries Engineering Services and Semiconductor Manufacturing
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Location: San Jose, CA (other locations can be discussed)
Experience: 10–20 Years
About the Role Eximietas Design is seeking an Analog Layout Design Lead to drive the physical implementation of high‑performance analog and mixed‑signal IP, with strong emphasis on High‑Speed SerDes PHYs (28G/56G/112G+) in advanced FinFET nodes (7nm, 5nm, and below).
This role is ideal for a hands‑on technical leader who has owned mission‑critical analog blocks, defined layout methodology, and consistently delivered first‑pass clean layouts with minimal ECOs. You will partner closely with circuit design, PD, and verification teams while mentoring layout engineers and influencing layout strategy across projects.
Key Responsibilities
Lead and own analog / mixed‑signal layout architecture for complex IP and SerDes macros.
Execute and review layouts for TX/RX, clock paths, PLL/DLL/CDR, IOs, regulators, bias circuits, and analog datapaths.
Define and enforce layout methodology including:
Precision matching, symmetry, shielding, and isolation
Parasitic optimization and noise mitigation
Power grid design, routing guides, density strategies, and metal fill solutions
Drive floorplanning and hierarchical layout strategies to optimize analog performance and scalability.
Ensure clean signoff across DRC, LVS, ERC, density, extraction, EM/IR, and reliability flows.
Collaborate with PD teams on macro integration and full‑chip assembly.
Develop or enhance PCell libraries and SKILL‑based automation to improve layout productivity and consistency.
Mentor and technically guide junior and mid‑level layout engineers across global teams.
Support silicon debug and correlation, identifying layout‑driven performance issues.
Required Skills & Experience
10–20 years of hands‑on experience in custom analog / mixed‑signal IC layout.
Proven leadership owning high‑impact analog layouts from concept through tape‑out.
Deep expertise in High‑Speed SerDes layout (28G/56G/112G+ preferred).
Strong experience across advanced process nodes (FinFET 7nm/5nm and below).
Mastery of:
Precision matching and device placement
High‑current and clock‑sensitive structures
Substrate noise, latch‑up, ESD, and reliability considerations
Extensive experience with Cadence Virtuoso, Calibre / Synopsys verification flows, and extraction tools.
Proficiency in SKILL scripting, PCell development, and layout automation.
Track record of delivering first‑pass clean layouts with disciplined scheduling.
Strong communication, problem‑solving, and cross‑functional collaboration skills.
Nice to Have
Experience defining organization‑wide layout methodology or training programs.
Prior ownership of PLL, clocking IP, or SerDes clock paths.
Exposure to post‑silicon validation and layout‑related debug.
Experience working with distributed or offshore layout teams.
Familiarity with PCIe, Ethernet, CXL, or similar high‑speed protocols.
Why Join Eximietas?
Work on next‑generation SerDes and analog IP in leading‑edge nodes.
Take on a technical leadership role with high ownership and visibility.
Influence layout methodology and best practices across projects.
Collaborate with top‑tier semiconductor teams in California and Texas.
Apply or refer at
mohini.tyagi@eximietas.design
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Engineering, Research, and Consulting
Industries Engineering Services and Semiconductor Manufacturing
#J-18808-Ljbffr