Lattice Semiconductor
Sr Technical Marketing Architect – Datacenter & AI Systems
Lattice Semiconductor, San Jose, California, United States, 95199
Overview
Lattice Semiconductor is a globally recognized developer of programmable logic solutions that are transforming the semiconductor industry. We focus on R&D, product innovation, and customer service. Our culture values teamwork, enthusiasm, and results‑oriented execution.
Responsibilities
Architect datacenter control solutions across compute, storage, and network domains including BMC, RMC, and rack orchestration.
Identify and define FPGA attach points for telemetry, power/cooling control, fabric management, and secure boot.
Shape technical marketing strategy for AI and datacenter platforms—developing MRDs, reference architectures, and partner programs.
Collaborate with SoC, CPU, DPU, and accelerator vendors to co‑design FPGA‑enhanced system solutions.
Engage with CSPs, OEMs, and ODMs to translate requirements into FPGA‑based proofs of concept.
Drive technical narratives that showcase Lattice leadership in control, security, and system orchestration.
Align with product and engineering teams to ensure design integrity, validation, and roadmap coherence.
Represent Lattice in OCP, DMTF, and related forums to guide standards and influence ecosystem direction.
Required Qualifications
BS/MS in Electrical, Computer, or Systems Engineering.
12+ years in datacenter hardware architecture, technical marketing, or system design.
Expertise in platform manageability and control (BMC, RMC, attestation, telemetry).
Knowledge of datacenter storage, networking, and power systems (PCIe/CXL, NVMe, Ethernet, cooling).
Familiarity with LTPI, SPDM, PLDM, and other DMTF and OCP standards.
Proven ability to translate architectures into strategies and drive ecosystem adoption.
Experience working with hyperscalers, OEMs, or SoC vendors on validation and deployment.
Excellent communication and executive presentation skills.
Preferred Qualifications
Experience in rack‑scale orchestration, AI cluster, or fabric management.
Knowledge of FPGA/CPLD integration in control, telemetry, or security roles.
Understanding of AI server architectures, accelerators, and thermal/power management.
Published contributions to industry standards or specifications.
Benefits The base pay for this role is between $180,000 to $230,000 per year in the Bay Area. Compensation will align with local markets elsewhere. In addition to base salary, we offer an incentive plan bonus and new‑hire equity for a competitive total compensation package.
Lattice offers a comprehensive compensation and benefits program designed to attract, retain, motivate, reward, and celebrate the highest caliber employees. Our global workforce shares a total commitment to customer success and an unbending will to win.
Applications are welcome from all qualified candidates.
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Responsibilities
Architect datacenter control solutions across compute, storage, and network domains including BMC, RMC, and rack orchestration.
Identify and define FPGA attach points for telemetry, power/cooling control, fabric management, and secure boot.
Shape technical marketing strategy for AI and datacenter platforms—developing MRDs, reference architectures, and partner programs.
Collaborate with SoC, CPU, DPU, and accelerator vendors to co‑design FPGA‑enhanced system solutions.
Engage with CSPs, OEMs, and ODMs to translate requirements into FPGA‑based proofs of concept.
Drive technical narratives that showcase Lattice leadership in control, security, and system orchestration.
Align with product and engineering teams to ensure design integrity, validation, and roadmap coherence.
Represent Lattice in OCP, DMTF, and related forums to guide standards and influence ecosystem direction.
Required Qualifications
BS/MS in Electrical, Computer, or Systems Engineering.
12+ years in datacenter hardware architecture, technical marketing, or system design.
Expertise in platform manageability and control (BMC, RMC, attestation, telemetry).
Knowledge of datacenter storage, networking, and power systems (PCIe/CXL, NVMe, Ethernet, cooling).
Familiarity with LTPI, SPDM, PLDM, and other DMTF and OCP standards.
Proven ability to translate architectures into strategies and drive ecosystem adoption.
Experience working with hyperscalers, OEMs, or SoC vendors on validation and deployment.
Excellent communication and executive presentation skills.
Preferred Qualifications
Experience in rack‑scale orchestration, AI cluster, or fabric management.
Knowledge of FPGA/CPLD integration in control, telemetry, or security roles.
Understanding of AI server architectures, accelerators, and thermal/power management.
Published contributions to industry standards or specifications.
Benefits The base pay for this role is between $180,000 to $230,000 per year in the Bay Area. Compensation will align with local markets elsewhere. In addition to base salary, we offer an incentive plan bonus and new‑hire equity for a competitive total compensation package.
Lattice offers a comprehensive compensation and benefits program designed to attract, retain, motivate, reward, and celebrate the highest caliber employees. Our global workforce shares a total commitment to customer success and an unbending will to win.
Applications are welcome from all qualified candidates.
#J-18808-Ljbffr