Senior ASIC Cache Architect & RTL Designer

A leading technology company is seeking a Senior ASIC Design Engineer to design and develop hardware for cache subsystems within high-performance systems on a chip (SoC). Candidates should have over 10 years of experience with ASIC design, particularly in memory systems and cache design. This role offers a competitive salary range between $181,100 and $318,400, along with comprehensive benefits including medical coverage, retirement benefits, and opportunities for stock participation.
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