RFIC Layout Engineer — High-Impact Wireless SoCs

A leading technology company in San Francisco is looking for an RFIC Layout Engineer to design state-of-the-art CMOS radios. Key responsibilities include transistor-level layout, working with designers on floorplanning, and review of routing for RF blocks. Candidates should have a BS degree and 3+ years of experience in RFIC layout. This role offers a competitive salary range of $141,800 to $258,600 along with comprehensive benefits including medical coverage and stock programs.
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