Senior Analog PLL Design Engineer (FinFET)

A leading semiconductor company is looking for an experienced Circuit Design Engineer to join their PLL design team in Santa Clara, CA. The ideal candidate will possess solid knowledge in mixed signal circuit design, specifically in PLLs, and experience in the semiconductor industry. Responsibilities include designing complex building blocks, running verification flows, and mentoring junior engineers. Candidates should hold a Master's in electrical engineering and demonstrate strong communication and analytical skills. Join a dynamic team and advance your career in an innovative environment. #J-18808-Ljbffr