Senior Serdes Layout Engineer — High-Speed PHY, Onsite

A leading semiconductor firm in San Jose is seeking a Senior Staff Engineer for Serdes Layout Design. This role requires extensive experience in high-speed mixed-signal layout, knowledge of CMOS technologies, and the ability to collaborate effectively with circuit designers. The ideal candidate will have a strong background in layout optimization and will be involved in innovative projects within a flexible work environment. Benefits include generous paid time off and support for emotional wellness. #J-18808-Ljbffr