FinFET IC Layout Architect – Analog/RF at 3nm

A leading engineering firm in Irvine, CA seeks a skilled designer for their IC layout team. This full-time position involves collaboration on next-generation products for commercial, civil, and space missions. Candidates should possess strong analog layout skills, expertise with Cadence Virtuoso, and experience in advanced node IC layout down to 3 nm. Comprehensive benefits including 15 days PTO, medical benefits, and more are offered, with an annual salary between $130,000 and $160,000. #J-18808-Ljbffr