Senior ASIC Designer - RTL/Timing, Floorplan & Closure Lead

A leading technology company in Sunnyvale, California, is seeking an experienced engineer to join their Physical design team. This role focuses on optimizing floorplan and timing closure while validating designs with the Verification team. The ideal candidate will have a Bachelor's degree in Electrical Engineering, over 10 years of experience, and strong analytical skills alongside proficiency in Verilog and System Verilog. This position offers a collaborative environment that prioritizes innovation and growth.
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