Verification Engineer II - IP/SoC Pre-Silicon (UVM)

A leading semiconductor company in Chandler, Arizona is seeking an Engineer II – Verification. The successful candidate will be responsible for IP level pre-silicon verification using UVM/SystemVerilog methodologies, collaborating with global teams to ensure comprehensive verification. Candidates should have a relevant degree and 1-2 years of experience in ASIC/SoC functional verification. This position offers competitive compensation, including a base salary range of $70,304 - $143,000, along with health benefits and retirement plans. #J-18808-Ljbffr