Senior Analog IC Layout Engineer – finFET, 16nm, 25Gbps

A leading technology recruitment partner is seeking a Senior Analog IC Layout Engineer with extensive experience in analog IC layout, particularly in high-speed designs and finFET technology. The ideal candidate should have a minimum of 7 years' experience and be proficient in using Cadence tools. This position offers an attractive salary and the opportunity to work on cutting-edge projects in the semiconductor industry. #J-18808-Ljbffr