Numem
Senior Layout Engineer (Memory / Mixed-Signal SoC)
Numem, Arizona City, Arizona, United States, 85123
Numem is a California- and Arizona-based company that transforms next-generation memory technologies to power AI applications at the edge and data center. Our solutions deliver ultra-low latency, low power, and optimized density to meet the performance demands of modern AI workloads. We specialize in advancing founder-based MRAM technologies, enhanced through state-of-the-art innovations in design, sense, power efficiency, and performance optimization, enabling a broad range of applications across edge and data-center environments
*Mesa, Arizona Site Preferred*
Role Summary
We are seeking a Senior Layout Engineer to lead physical implementation of a complex memory-centric mixed-signal chip through multiple tapeout milestones. The role includes hands-on full-custom layout, block integration, and top-level assembly spanning memory arrays, analog/mixed-signal blocks, digital logic, place-and-route, and IO/ESD structures. You will partner with Memory, Analog, and Digital Design teams to ensure layout quality, reliability, performance, and manufacturability across foundry signoff requirements.
Key Responsibilities
* Lead full-custom layout for memory, analog/mixed-signal, and mixed-voltage interface circuitry. * Integrate and assemble top-level chip/block hierarchies including memory macros, analog slices, digital logic, and IO/ESD. * Drive floorplanning, power-grid planning, shielding, and critical routing strategies for performance and noise robustness. * Coordinate with digital P&R teams and ensure clean handoff between custom and P&R regions (boundaries, pins, blockages). * Own layout signoff readiness: DRC/LVS, density/fill, antenna, EM/IR, ESD, and reliability checks. * Work closely with design engineers to interpret constraints (matching, symmetry, device orientation, guardringing). * Manage iterative ECOs and integration changes while maintaining schedule and quality targets. * Develop scripts/automation (TCL/Python/Shell) to improve productivity for repetitive layout and QA flows.
Required Qualifications
* 10+ years of hands-on IC layout experience with multiple successful tapeouts (memory or mixed-signal preferred). * Demonstrated experience leading block-level and top-level integration including custom + P&R + IO/ESD domains. * Must be knowledgeable of basic layout and design tools * Strong understanding of layout-dependent effects and analog layout fundamentals (matching, parasitics, shielding, guard rings). * Experience with multi-voltage domains, isolation techniques, and reliable power routing methodologies. * Expertise running and debugging signoff flows: DRC/LVS, parasitic extraction, EM/IR, antenna, and reliability checks. * Ability to communicate effectively with Memory, Analog, and Digital design teams and drive closure on layout issues.
Tools & Environment
* Cadence: Virtuoso Layout Suite / Custom Compiler equivalents; familiarity with OA libraries and hierarchical flows. * Synopsys: Custom Compiler / ICC2 or equivalent digital implementation tools; ability to collaborate with P&R teams. * Verification/Signoff: Calibre or equivalent DRC/LVS/PERC; extraction and post-layout simulation workflows. * Automation: TCL/Python/Shell scripting to automate layout tasks, checks, pinlist generation, and QA.
Preferred Qualifications
* Experience integrating memory arrays/macros with shared analog and IO infrastructure. * Familiarity with ESD methodology and IO ring integration constraints. * Experience with high-density routing, noise isolation, and substrate coupling mitigation. * Comfortable mentoring junior layout engineers and driving quality checklists.
Job Type: Full-time
Pay: $120,000.00 - $170,000.00 per year
Benefits: * Dental insurance * Health insurance * Paid time off * Vision insurance
Work Location: In person by Jobble
*Mesa, Arizona Site Preferred*
Role Summary
We are seeking a Senior Layout Engineer to lead physical implementation of a complex memory-centric mixed-signal chip through multiple tapeout milestones. The role includes hands-on full-custom layout, block integration, and top-level assembly spanning memory arrays, analog/mixed-signal blocks, digital logic, place-and-route, and IO/ESD structures. You will partner with Memory, Analog, and Digital Design teams to ensure layout quality, reliability, performance, and manufacturability across foundry signoff requirements.
Key Responsibilities
* Lead full-custom layout for memory, analog/mixed-signal, and mixed-voltage interface circuitry. * Integrate and assemble top-level chip/block hierarchies including memory macros, analog slices, digital logic, and IO/ESD. * Drive floorplanning, power-grid planning, shielding, and critical routing strategies for performance and noise robustness. * Coordinate with digital P&R teams and ensure clean handoff between custom and P&R regions (boundaries, pins, blockages). * Own layout signoff readiness: DRC/LVS, density/fill, antenna, EM/IR, ESD, and reliability checks. * Work closely with design engineers to interpret constraints (matching, symmetry, device orientation, guardringing). * Manage iterative ECOs and integration changes while maintaining schedule and quality targets. * Develop scripts/automation (TCL/Python/Shell) to improve productivity for repetitive layout and QA flows.
Required Qualifications
* 10+ years of hands-on IC layout experience with multiple successful tapeouts (memory or mixed-signal preferred). * Demonstrated experience leading block-level and top-level integration including custom + P&R + IO/ESD domains. * Must be knowledgeable of basic layout and design tools * Strong understanding of layout-dependent effects and analog layout fundamentals (matching, parasitics, shielding, guard rings). * Experience with multi-voltage domains, isolation techniques, and reliable power routing methodologies. * Expertise running and debugging signoff flows: DRC/LVS, parasitic extraction, EM/IR, antenna, and reliability checks. * Ability to communicate effectively with Memory, Analog, and Digital design teams and drive closure on layout issues.
Tools & Environment
* Cadence: Virtuoso Layout Suite / Custom Compiler equivalents; familiarity with OA libraries and hierarchical flows. * Synopsys: Custom Compiler / ICC2 or equivalent digital implementation tools; ability to collaborate with P&R teams. * Verification/Signoff: Calibre or equivalent DRC/LVS/PERC; extraction and post-layout simulation workflows. * Automation: TCL/Python/Shell scripting to automate layout tasks, checks, pinlist generation, and QA.
Preferred Qualifications
* Experience integrating memory arrays/macros with shared analog and IO infrastructure. * Familiarity with ESD methodology and IO ring integration constraints. * Experience with high-density routing, noise isolation, and substrate coupling mitigation. * Comfortable mentoring junior layout engineers and driving quality checklists.
Job Type: Full-time
Pay: $120,000.00 - $170,000.00 per year
Benefits: * Dental insurance * Health insurance * Paid time off * Vision insurance
Work Location: In person by Jobble