Advanced Micro Devices
Senior Staff Pre‑Silicon Power Modeling Lead — x86 SoCs
Advanced Micro Devices, Austin, Texas, us, 78716
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
Senior Staff Pre‑Silicon Power Modeling Lead — x86 SoCs THE ROLE AMD’s embedded and client x86 programs demand first‑time‑right silicon. You will lead
SoC‑level pre‑silicon power modeling —owning the methodology, models, and cross‑functional influence that translate into accurate
Perf/Watt
projections, robust
DVFS/AVFS
plans, and silicon correlation that de‑risks program power budgets.
THE PERSON
B.S./M.S. in EE/CE/CS (or related) with
10+ years
in SoC
pre‑silicon power modeling/estimation
and cross‑domain collaboration.
Demonstrated experience building
top‑level SoC power models
with high correlation to silicon, including IP‑level VBM integration and workload‑based projections.
Hands‑on with
EDA/tooling : PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation.
Deep knowledge of
x86 micro‑architecture
(CPU pipelines, caches),
GPU/NPU
basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions.
Proven ability to define
DVFS/AVFS
strategies and drive FW telemetry requirements; familiarity with
EDC/TDC/CaC
semantics and their impact on power.
A validated
SoC power model & scorecard
that anchors program power budgets and executive reviews.
Workload‑specific DVFS/AVFS tables
and telemetry specs for FW/BIOS enablement.
Correlation reports
(estimated vs. measured) and recommendations that accelerate first‑time‑right silicon.
KEY RESPONSIBILITIES
Own the SoC power model
end‑to‑end using AMD’s converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O.
Define
use‑case power envelopes
across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs.
Drive
DVFS/AVFS strategy
(P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS.
Establish
IP/subsystem power budgets ; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations).
Build repeatable
model‑to‑silicon correlation
plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews.
Lead
tool flows & automation
(e.g., PowerArtist, PrimeTime PX; Python‑based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders.
Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure
converged Perf/Watt outcomes
from concept through bring‑up.
PREFERRED EXPERIENCE
Segment experience modeling power for
automotive (AEC‑Q100/ASIL) use‑cases ,
networking
throughput workloads,
storage
I/O patterns,
industrial/robotics
duty cycles.
System performance modeling familiarity (GEM5/Simics/SystemC) to align Perf/Watt predictions and bottleneck analysis with architecture teams.
Experience creating
PnP dashboards/regressions
(Python/Jenkins/Grafana/InfluxDB) for continuous tracking.
ACADEMIC CREDENTIALS
B.S./M.S. in EE/CE/CS (or related) with strong industry experience in SoC
pre‑silicon power modeling/estimation
and cross‑domain collaboration.
LOCATION Austin, TX (Hybrid)
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
#J-18808-Ljbffr
At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
Senior Staff Pre‑Silicon Power Modeling Lead — x86 SoCs THE ROLE AMD’s embedded and client x86 programs demand first‑time‑right silicon. You will lead
SoC‑level pre‑silicon power modeling —owning the methodology, models, and cross‑functional influence that translate into accurate
Perf/Watt
projections, robust
DVFS/AVFS
plans, and silicon correlation that de‑risks program power budgets.
THE PERSON
B.S./M.S. in EE/CE/CS (or related) with
10+ years
in SoC
pre‑silicon power modeling/estimation
and cross‑domain collaboration.
Demonstrated experience building
top‑level SoC power models
with high correlation to silicon, including IP‑level VBM integration and workload‑based projections.
Hands‑on with
EDA/tooling : PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation.
Deep knowledge of
x86 micro‑architecture
(CPU pipelines, caches),
GPU/NPU
basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions.
Proven ability to define
DVFS/AVFS
strategies and drive FW telemetry requirements; familiarity with
EDC/TDC/CaC
semantics and their impact on power.
A validated
SoC power model & scorecard
that anchors program power budgets and executive reviews.
Workload‑specific DVFS/AVFS tables
and telemetry specs for FW/BIOS enablement.
Correlation reports
(estimated vs. measured) and recommendations that accelerate first‑time‑right silicon.
KEY RESPONSIBILITIES
Own the SoC power model
end‑to‑end using AMD’s converged methodology, delivering accurate workload‑based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O.
Define
use‑case power envelopes
across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs.
Drive
DVFS/AVFS strategy
(P‑states, C‑states, voltage/frequency points), telemetry requirements, and FW hand‑offs based on model outputs; provide early tables and guardrails to FW/BIOS.
Establish
IP/subsystem power budgets ; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations).
Build repeatable
model‑to‑silicon correlation
plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews.
Lead
tool flows & automation
(e.g., PowerArtist, PrimeTime PX; Python‑based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders.
Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure
converged Perf/Watt outcomes
from concept through bring‑up.
PREFERRED EXPERIENCE
Segment experience modeling power for
automotive (AEC‑Q100/ASIL) use‑cases ,
networking
throughput workloads,
storage
I/O patterns,
industrial/robotics
duty cycles.
System performance modeling familiarity (GEM5/Simics/SystemC) to align Perf/Watt predictions and bottleneck analysis with architecture teams.
Experience creating
PnP dashboards/regressions
(Python/Jenkins/Grafana/InfluxDB) for continuous tracking.
ACADEMIC CREDENTIALS
B.S./M.S. in EE/CE/CS (or related) with strong industry experience in SoC
pre‑silicon power modeling/estimation
and cross‑domain collaboration.
LOCATION Austin, TX (Hybrid)
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
#J-18808-Ljbffr