Junior Analog Layout Designer: High-Speed CMOS IP

A global technology company is seeking an entry-level Custom Layout Designer to implement high-speed and high-accuracy cells and collaborate with teams worldwide. Candidates should have a BSEE or MSEE and exposure to microelectronics design. Knowledge of analog layout techniques and Cadence Virtuoso tools is advantageous. Join us to help solve challenging problems in the tech industry and work on cutting-edge technologies. #J-18808-Ljbffr