This range is provided by Langham Recruitment. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$240,000.00/yr - $300,000.00/yr
Senior Engineering Director – High-Speed Silicon & Photonic Integration
Full-Time | Onsite/Hybrid | Competitive Compensation + Bonus + Equity + Benefits
We’re hiring a Senior Engineering Director to lead advanced-node semiconductor development for next‑generation high‑speed networking. You’ll guide multidisciplinary teams across digital, analog, and photonic domains, driving full‑flow silicon execution and delivering high‑performance, high‑reliability mixed‑signal solutions.
Key Responsibilities
- Lead full‑chip programs from architecture through tape‑out (RTL → PD → sign‑off → GDSII).
- Direct development of high‑speed analog drivers, TIAs, and SerDes (NRZ/PAM4).
- Oversee electrical–optical co‑design with photonics teams.
- Own post‑silicon validation, ATE strategy, and system bring‑up.
- Hire, mentor, and scale engineering teams; build processes and execution rigor.
- Manage vendors, IP partners, and multi‑million‑dollar silicon budgets.
Qualifications
- 15+ years in semiconductor design; 5+ years in engineering leadership.
- Proven tape‑outs of high‑speed analog blocks for optical or networking systems.
- Deep expertise in SerDes and advanced CMOS nodes (≤7 nm).
- Mastery of Synopsys (digital), Cadence Innovus/Tempus (PD), and Cadence Virtuoso/Spectre (analog).
- Strong organizational leadership and program management experience.
What We Offer
- Competitive compensation + Bonus + Equity + Full Benefits.
- Leadership role shaping next‑generation high‑speed compute and networking hardware.
- Opportunity to build and scale world‑class silicon and photonics engineering teams.
Senior level: Director
Employment type: Full‑time
Job function: Engineering and Management
Industries: Semiconductor Manufacturing and Appliances, Electrical, and Electronics Manufacturing
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