Remote Senior High-Speed Analog Layout Architect

A leading technology recruitment firm is seeking a Senior High-Speed Analog Layout Engineer to lead the physical layout design of complex analog/mixed-signal macros. The ideal candidate will have over 5 years of hands-on experience with TSMC FinFET process nodes and proven leadership in major IP layout macros. This role requires strong expertise in layout best practices, excellent documentation and communication skills, and proficiency with industry-standard tools such as Cadence Virtuoso and Calibre. Join a dynamic team that values innovation and problem-solving in a fast-paced environment. #J-18808-Ljbffr