Expedite Talent Solutions
US_East | Electrical / Electronics & Semiconductors Engineer_L3
Expedite Talent Solutions, Santa Clara, California, us, 95053
US_East | Electrical / Electronics & Semiconductors Engineer L3
Location: Santa Clara, CA
Job Summary AMS CAD/Analog Engineer – 3‑month Contract to Hire (CTH) with no fees. Role focuses on supporting IC design teams in analog mixed‑signal flow automation, PDK administration, layout and verification flow support, and scripting development.
Responsibilities
Administer CAD EDA environment for analog and digital design teams.
Support design flows from EDA vendors such as Cadence, Synopsys, Mentor, Keysight, Ansys.
Write Python scripts to support design teams and flows.
Oversee physical verification tools and decks (DRC, LVS, Extraction, EM/IR, ESD) and customize as needed.
Develop and maintain infrastructure for custom PDK development (pcells, models, DRC, LVS).
Install and track foundry PDKs, creating automated regression testing.
Assist infrastructure team with computing resources availability and performance.
Qualifications
Bachelor’s or Master’s degree with 4+ years of CAD engineering experience.
Experience in scripting languages such as Python.
Proficiency in industry‑standard design software: Cadence Virtuoso, Cadence/Calibre DRC, LVS tools.
Experience supporting design teams with analog and digital design flows.
Strong communication skills and ability to work with remote teams.
Programming skills in SKILL, Perl (Python a plus).
Strong fundamentals in software development.
Solid experience with EMIR (RV) and physical design verification tools (DRC/LVS/PEX/ERC).
Mandatory Skills & Proficiency
Cadence/Synopsys/Mentor Analog layout tools – Preference 5
Python – Preference 3
Keysight/Ansys tools – Preference 5
Seniority Level Mid‑Senior Level
Employment Type Full‑Time
Job Function Other
Industries Civil Engineering
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Job Summary AMS CAD/Analog Engineer – 3‑month Contract to Hire (CTH) with no fees. Role focuses on supporting IC design teams in analog mixed‑signal flow automation, PDK administration, layout and verification flow support, and scripting development.
Responsibilities
Administer CAD EDA environment for analog and digital design teams.
Support design flows from EDA vendors such as Cadence, Synopsys, Mentor, Keysight, Ansys.
Write Python scripts to support design teams and flows.
Oversee physical verification tools and decks (DRC, LVS, Extraction, EM/IR, ESD) and customize as needed.
Develop and maintain infrastructure for custom PDK development (pcells, models, DRC, LVS).
Install and track foundry PDKs, creating automated regression testing.
Assist infrastructure team with computing resources availability and performance.
Qualifications
Bachelor’s or Master’s degree with 4+ years of CAD engineering experience.
Experience in scripting languages such as Python.
Proficiency in industry‑standard design software: Cadence Virtuoso, Cadence/Calibre DRC, LVS tools.
Experience supporting design teams with analog and digital design flows.
Strong communication skills and ability to work with remote teams.
Programming skills in SKILL, Perl (Python a plus).
Strong fundamentals in software development.
Solid experience with EMIR (RV) and physical design verification tools (DRC/LVS/PEX/ERC).
Mandatory Skills & Proficiency
Cadence/Synopsys/Mentor Analog layout tools – Preference 5
Python – Preference 3
Keysight/Ansys tools – Preference 5
Seniority Level Mid‑Senior Level
Employment Type Full‑Time
Job Function Other
Industries Civil Engineering
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