Astera Labs is hiring: ASIC Design Director (San Jose) in San Jose

Join to apply for the ASIC Design Director role at Astera Labs

Astera Labs (NASDAQ: ALAB) provides rackscale AI infrastructure through purposebuilt connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductorbased technologies with the companys COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver endtoend scaleup and scaleout connectivity. The companys custom connectivity solutions business complements its standardsbased portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at

Job Description

We are seeking a Director of Digital Design Engineering to lead the microarchitecture, RTL implementation, and frontend development of highperformance connectivity solutions for nextgeneration network controllers. The ideal candidate has deep expertise in frontend ASIC design, strong leadership experience, and a solid understanding of communication and interface standards such as PCIe, Ethernet, and UALink. This role requires onsite presence.

Basic Qualifications

• Bachelors degree in Electrical or Computer Engineering required; Masters degree preferred.
• 12+ years of experience developing or supporting complex SoC/silicon products for server, storage, or networking applications.
• 5+ years of technical leadership or engineering management experience.
• Strong professional presence with the ability to manage multiple priorities, prepare for and lead customer discussions, and operate independently with minimal supervision.
• Entrepreneurial, openminded, and actionoriented mindset with a strong customer focus.
• Authorized to work in the U.S. and able to start immediately.

Required Experience

• Handson experience and strong working knowledge of Ethernet or UALink.
• Solid understanding of packetbased switching architectures and network protocol processing.
• Proven experience with switch fabrics, crossbar architecture, and highspeed memory subsystems.
• Familiarity with highspeed interconnect protocols such as Ethernet, UALink, Infinity Fabric, NVLink, or HyperTransport.
• Strong frontend design expertise including architecture, RTL development, simulation, synthesis, timing closure, GLS, and DFT.
• Demonstrated ownership of fullchip or blocklevel development from architecture through GDS, delivering multiple complex designs into production, working closely with both hardware and software teams.
• Experience with Cadence and/or Synopsys digital design and DFT tool flows.
• Knowledge of DFT methodologies, including stuckat and transition fault scan insertion.
• Expertise in silicon bringup, performance tuning, and labbased debug using equipment such as logic analyzers, scopes, protocol analyzers, and highspeed test setups.
• Experience working with advanced technology nodes (5nm or below).

Preferred Experience

• Proficiency in scripting languages such as Python or equivalent.
• Experience developing or supporting PCIe, Ethernet, or DDRbased products; familiarity with securityrelated standards.
• Background in developing ASIC design methodologies and driving methodology adoption across teams.

Salary

Base salary range: $218,500USD$260,000USD, determined based on location, experience, and similar roles. This position may be hired as a Senior Manager Level or Director Level.

Diversity & Inclusion

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and nonbinary people, veterans, parents, and individuals with disabilities.

#J-18808-Ljbffr