Lead AMS Layout Engineer — High-Density Power ICs

A power management technology leader in Silicon Valley seeks an experienced Analog/Mixed-Signal Layout Engineer. This role focuses on high-performance power management ICs, where candidates will execute full-custom layouts and collaborate closely with circuit designers to optimize designs. Ideal candidates have 5+ years of experience with deep expertise in custom analog layout and strong proficiency in Cadence Virtuoso. This position offers the chance to thrive in a dynamic, high-accountability culture in the heart of AI technology. #J-18808-Ljbffr