IC Layout Engineer
Qorvo, Inc., Richardson, TX, United States
IC Layout Engineer
Experience Level: Professional
Job Type: Regular
Location: Richardson, TX, US, 75081
Requisition ID: 10029
The IC Layout Engineer position within the High Performance Analog (HPA) division is responsible for developing and verifying integrated‑circuit (IC) layouts in close collaboration with design engineers, supporting programs from initial floorplanning through tapeout. The position uses industry‑standard EDA tools to complete schematic capture, physical verification (DRC/LVS), and documentation in support of GaAs, Silicon, and GaN technologies.
This is a hybrid position where the expectation is to be onsite in our Richardson TX office a minimum of four days a week.
Responsibilities
Partner with design engineers to develop IC layouts from initial floorplan through tapeout.
Create cell‑level and chip‑level layouts, including placement, routing, and hierarchy management.
Perform schematic entry and layout‑versus‑schematic (LVS) and design‑rule‑check (DRC) verification; resolve issues to closure.
Use EDA tool Keysight ADS for schematic capture, layout, and physical verification.
Support multiple semiconductor technologies (GaAs, Silicon, and GaN)
Create laminate/substrate designs and assembly drawings as needed to support packaging and integration.
Develop and maintain documentation and training materials to support engineering workflows and best practices.
Required Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
2+ years of IC layout experience, including schematic‑driven layout and physical verification (DRC/LVS).
Experience using Keysight ADS.
Ability to quickly learn new process design kits (PDKs), design rules, and internal workflows.
Self‑motivated and detail‑oriented, with strong communication, analytical, and collaboration skills.
Ability to work effectively both independently and as part of a cross‑functional team.
Preferred Qualifications
Experience with GaAs, GaN and Silicon processes.
Experience using Cadence AWR, and Cadence Virtuoso
Demonstrated attention to detail and commitment to producing high‑quality deliverables in an R&D environment.
Working knowledge of Windows and Linux environments.
This position is not eligible for visa sponsorship by the Company.
We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.
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Job Type: Regular
Location: Richardson, TX, US, 75081
Requisition ID: 10029
The IC Layout Engineer position within the High Performance Analog (HPA) division is responsible for developing and verifying integrated‑circuit (IC) layouts in close collaboration with design engineers, supporting programs from initial floorplanning through tapeout. The position uses industry‑standard EDA tools to complete schematic capture, physical verification (DRC/LVS), and documentation in support of GaAs, Silicon, and GaN technologies.
This is a hybrid position where the expectation is to be onsite in our Richardson TX office a minimum of four days a week.
Responsibilities
Partner with design engineers to develop IC layouts from initial floorplan through tapeout.
Create cell‑level and chip‑level layouts, including placement, routing, and hierarchy management.
Perform schematic entry and layout‑versus‑schematic (LVS) and design‑rule‑check (DRC) verification; resolve issues to closure.
Use EDA tool Keysight ADS for schematic capture, layout, and physical verification.
Support multiple semiconductor technologies (GaAs, Silicon, and GaN)
Create laminate/substrate designs and assembly drawings as needed to support packaging and integration.
Develop and maintain documentation and training materials to support engineering workflows and best practices.
Required Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
2+ years of IC layout experience, including schematic‑driven layout and physical verification (DRC/LVS).
Experience using Keysight ADS.
Ability to quickly learn new process design kits (PDKs), design rules, and internal workflows.
Self‑motivated and detail‑oriented, with strong communication, analytical, and collaboration skills.
Ability to work effectively both independently and as part of a cross‑functional team.
Preferred Qualifications
Experience with GaAs, GaN and Silicon processes.
Experience using Cadence AWR, and Cadence Virtuoso
Demonstrated attention to detail and commitment to producing high‑quality deliverables in an R&D environment.
Working knowledge of Windows and Linux environments.
This position is not eligible for visa sponsorship by the Company.
We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.
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