Senior Mixed-Signal IP Designer: RTL Focus

A leading semiconductor company is seeking a Senior Mixed-Signal IP Design Engineer in Austin, TX. In this role, you will leverage your 5+ years of industry experience in RTL design to develop high-quality SystemVerilog RTL. Collaborating with analog and digital design teams, you'll analyze performance bottlenecks and build architectural models. This position offers a competitive salary range of $128,600-$203,600 and comprehensive benefits including health insurance and a 401(k) plan. #J-18808-Ljbffr