
Senior Director of Engineering (High-Speed SERDES)
SBT, San Francisco, CA, United States
SBT is the exclusive executive recruiting firm for this confidential position.
Company Overview
This confidential, well-funded startup company is developing next-generation solutions aimed at solving bandwidth and connectivity challenges in advanced computing systems. Their core technology enables high-speed, scalable data movement to support emerging infrastructure demands that power AI workloads. Role Responsibilities
Silicon Development Ownership:
Lead and deliver complex, advanced-node semiconductor programs from architectural definition through tape-out and production readiness, ensuring technical rigor, schedule alignment, and execution quality across all design phases. High-Speed Interface & Photonic Co-Design:
Provide technical leadership for high-speed electrical and electro-optical interfaces, including SerDes, optical driver, and receiver architectures. Partner closely with photonics teams to establish robust co-design practices spanning electrical, optical, and packaging domains. Design Execution & Silicon Validation:
Define and oversee end-to-end design and verification workflows across digital, analog, and physical domains, from early implementation through signoff and silicon handoff. Lead post-silicon bring-up, characterization, and debug of high-speed interfaces, ensuring performance targets are met and enabling reliable system integration and production readiness. External Partnerships & Execution Governance:
Manage relationships with foundries, OSATs, IP vendors, and external engineering partners, setting clear milestones and accountability to support cost control, risk mitigation, and on-time delivery. Qualifications
10+ years of experience in semiconductor engineering, with a history of increasing technical and organizational responsibility across advanced-node silicon development programs. 3+ years of experience in senior-level management, building out a design organization from scratch Advanced technical engineering degree (MSEE, PhD) Proven expertise with leading end-to-end chip tape-out processes
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This confidential, well-funded startup company is developing next-generation solutions aimed at solving bandwidth and connectivity challenges in advanced computing systems. Their core technology enables high-speed, scalable data movement to support emerging infrastructure demands that power AI workloads. Role Responsibilities
Silicon Development Ownership:
Lead and deliver complex, advanced-node semiconductor programs from architectural definition through tape-out and production readiness, ensuring technical rigor, schedule alignment, and execution quality across all design phases. High-Speed Interface & Photonic Co-Design:
Provide technical leadership for high-speed electrical and electro-optical interfaces, including SerDes, optical driver, and receiver architectures. Partner closely with photonics teams to establish robust co-design practices spanning electrical, optical, and packaging domains. Design Execution & Silicon Validation:
Define and oversee end-to-end design and verification workflows across digital, analog, and physical domains, from early implementation through signoff and silicon handoff. Lead post-silicon bring-up, characterization, and debug of high-speed interfaces, ensuring performance targets are met and enabling reliable system integration and production readiness. External Partnerships & Execution Governance:
Manage relationships with foundries, OSATs, IP vendors, and external engineering partners, setting clear milestones and accountability to support cost control, risk mitigation, and on-time delivery. Qualifications
10+ years of experience in semiconductor engineering, with a history of increasing technical and organizational responsibility across advanced-node silicon development programs. 3+ years of experience in senior-level management, building out a design organization from scratch Advanced technical engineering degree (MSEE, PhD) Proven expertise with leading end-to-end chip tape-out processes
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