Senior PLL Design Engineer for Next-Gen Transceivers

Celero Communications is seeking a High-Speed CMOS PLL Analog Design Engineer to join their team in Irvine, CA. This role involves architecting and designing PLLs for advanced optical transceivers, while focusing on challenges in high-speed design and layout verification.
The ideal candidate will hold a Master’s degree or PhD in Electrical Engineering and have at least 5 years of experience in PLL design and node technologies. Strong proficiency in Cadence Virtuoso and excellent communication skills are essential for this pivotal role.

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