Digital Backend Design Intern — RTL & Cadence Flow

NXP Semiconductors in Chandler, AZ is seeking a Physical Design Intern to join a highly experienced team. You will work closely with engineers to gain hands-on experience in digital backend design.
You will understand the flow from Synthesis to GDS2 using Cadence tools, run experiments to find area-optimal RTL solutions, and study Cadence manuals to suggest improvements. On-site presence in Chandler for at least three days per week is expected.

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