Tenstorrent is seeking an engineer to lead the front-end RTL physical implementation for a high‑performance RISC‑V CPU. You will drive CAD flows, define floorplans, and collaborate with microarchitecture, RTL, and PD teams to optimize frequency, power, and area.
This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience and a compensation package reflecting base and variable components.
#J-18808-Ljbffr