Rivos Inc.
CPU Power Management and Debug Microarchitecture & Logic Design - Full Time
Rivos Inc., Fort Collins, Colorado, us, 80523
CPU Power Management and Debug Microarchitecture & Logic Design - Full Time
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CPU Power Management and Debug Microarchitecture & Logic Design - Full Time
role at
Rivos Inc.
Responsibilities
Develop microarchitecture specifications for power management and debug features
Own RTL development of power management and debug features
Collaborate with verification, physical implementation, DFT, and firmware teams to deliver a design meeting functional, performance, and power requirements
Work with external IP vendors to evaluate and integrate IP into the design
Apply domain knowledge to propose and evaluate new features
Requirements
Knowledge of modern OoO CPU microarchitectures
2+ years of relevant industry experience in CPU power management
Understanding of synchronous and asynchronous reset flows
Experience with active and idle power management techniques
Proficiency in SystemVerilog
Knowledge of coherent memory and bus protocols (AMBA, APB, SPI, I2C, etc.) is a plus
Knowledge of RISC-V ISA is a plus
Education Bachelor’s, Master’s, or PhD in EE or ECE
Seniority Level Entry level
Employment Type Full-time
Job Function Other
Industries Computer Hardware Manufacturing
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CPU Power Management and Debug Microarchitecture & Logic Design - Full Time
role at
Rivos Inc.
Responsibilities
Develop microarchitecture specifications for power management and debug features
Own RTL development of power management and debug features
Collaborate with verification, physical implementation, DFT, and firmware teams to deliver a design meeting functional, performance, and power requirements
Work with external IP vendors to evaluate and integrate IP into the design
Apply domain knowledge to propose and evaluate new features
Requirements
Knowledge of modern OoO CPU microarchitectures
2+ years of relevant industry experience in CPU power management
Understanding of synchronous and asynchronous reset flows
Experience with active and idle power management techniques
Proficiency in SystemVerilog
Knowledge of coherent memory and bus protocols (AMBA, APB, SPI, I2C, etc.) is a plus
Knowledge of RISC-V ISA is a plus
Education Bachelor’s, Master’s, or PhD in EE or ECE
Seniority Level Entry level
Employment Type Full-time
Job Function Other
Industries Computer Hardware Manufacturing
#J-18808-Ljbffr