Digital IP R&D Design Verification Methodology Technical Lead Job at Synopsys In

Digital IP R&D Design Verification Methodology Technical Lead

Join to apply for the Digital IP R&D Design Verification Methodology Technical Lead role at Synopsys Inc

Digital IP R&D Design Verification Methodology Technical Lead

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Join to apply for the Digital IP R&D Design Verification Methodology Technical Lead role at Synopsys Inc

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned verification expert with 15+ years in IP/SoC verification, skilled in System Verilog, UVM, and major Synopsys EDA tools. You thrive in complex environments, enjoy building scalable verification flows, and can independently own assignments. As a strong communicator and mentor, you support junior engineers and foster teamwork, always seeking innovative ways to improve verification methodologies and drive operational excellence at scale.

What You’ll Be Doing:

• Architect and develop reference verification flows for Synopsys Digital IPs using VCS, Verdi, and related tools.
• Build and standardize verification infrastructure and best practices.
• Mentor junior engineers and lead technical initiatives.
• Collaborate with cross-functional teams to align verification strategies.
• Integrate new tools, protocols, and automation scripts.
• Troubleshoot complex verification issues and ensure timely delivery.
  
  

The Impact You Will Have:

• Accelerate time to market for Synopsys IPs.
• Drive standardization and quality in verification processes.
• Lower project costs and risks through automation.
• Uplift product quality and reliability.
• Mentor and grow engineering talent.
• Influence EDA tool evolution and methodology direction.
  
  

What You’ll Need:

• 15+ years in digital IP/SoC verification with System Verilog/UVM.
• Deep expertise with Synopsys tools: VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP).
• Strong scripting skills (TCL, Python, or PERL).
• Knowledge of at least one interface protocol (PCIe, Ethernet, DDR, USB).
• Experience building scalable verification infrastructures.
  
  

Who You Are:

• Innovative, collaborative, and detail-oriented leader.
• Clear communicator and effective mentor.
• Resourceful, organized, and proactive in problem-solving.
  
  

The Team You’ll Be A Part Of:

Join our new Digital IP Verification Methodology COE, a team focused on creating and standardizing world-class verification flows for Synopsys digital IP.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Design, Consulting, and Engineering

• Industries

  Semiconductor Manufacturing, Software Development, and Computer Hardware Manufacturing

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