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eTeam

Chip Designer

eTeam, Santa Clara, California, us, 95053

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IC Packaging & Chiplet Integration

: 2.5D/3D packaging, flip-chip bonding, TSV, hybrid bonding Semiconductor Processing

: BEOL/FEOL integration, advanced interconnects, thin-film deposition (PVD, PECVD, ALD, CVD) Design & Simulation

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Siemens NX, Cadence, ANSYS, EasyEDA, ThermoCalc High-Speed I/O & Signal Integrity

: Impedance control, power/signal integrity, substrate optimization Process Development & Metrology

: DOE, SPC, FMEA, SEM, TEM, AFM, Raman spectroscopy Cross-Functional Collaboration

: Foundry/OSAT coordination, ASIC design support, product lifecycle management