Triple Crown
Title:
ASIC IP Integration Engineer
Company:
Triple Crown
Job Type:
Contract |
Duration:
9+ Months |
Location:
Remote |
Experience:
5+ years of relevant experience
Job Summary We are seeking an experienced ASIC IP Integration Engineer with strong expertise in SoC integration, interconnect design, and IP configuration using FlexNoC. The ideal candidate will be responsible for integrating complex IP blocks (AXI, DDR, PCIe, etc.) into ASIC designs, performing RTL-level design and verification, and ensuring successful synthesis and timing closure.
Responsibilities
Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
Develop and refine microarchitecture and infrastructure components for SoC-level integration.
Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
Collaborate cross-functionally with design, verification, and physical design teams.
Develop automation scripts in Python to streamline design, build, and verification flows.
Manage version control and collaboration using Git/GitHub.
Required Skills
RTL
FlexNoC
Timing Closure
Synthesis
LINT
CDC
ASIC
Benefits
Health, Dental and Vision Insurance
401(k)
Additional Information Referrals increase your chances of interviewing at Triple Crown by 2x.
#J-18808-Ljbffr
ASIC IP Integration Engineer
Company:
Triple Crown
Job Type:
Contract |
Duration:
9+ Months |
Location:
Remote |
Experience:
5+ years of relevant experience
Job Summary We are seeking an experienced ASIC IP Integration Engineer with strong expertise in SoC integration, interconnect design, and IP configuration using FlexNoC. The ideal candidate will be responsible for integrating complex IP blocks (AXI, DDR, PCIe, etc.) into ASIC designs, performing RTL-level design and verification, and ensuring successful synthesis and timing closure.
Responsibilities
Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
Develop and refine microarchitecture and infrastructure components for SoC-level integration.
Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
Collaborate cross-functionally with design, verification, and physical design teams.
Develop automation scripts in Python to streamline design, build, and verification flows.
Manage version control and collaboration using Git/GitHub.
Required Skills
RTL
FlexNoC
Timing Closure
Synthesis
LINT
CDC
ASIC
Benefits
Health, Dental and Vision Insurance
401(k)
Additional Information Referrals increase your chances of interviewing at Triple Crown by 2x.
#J-18808-Ljbffr