Arm
Principal Issue/Scheduler, Lead RTL Designer
Arm, Raleigh, North Carolina, United States, 27601
Principal Issue/Scheduler, Lead RTL Designer
Join to apply for the
Principal Issue/Scheduler, Lead RTL Designer
role at
Arm .
About Arm
Arm is the industry’s leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate.
Job Overview
The Issue/Scheduler unit is central to an out‑of‑order CPU’s performance and PPA. As the Principal (G6) for this unit you will take ownership of the RTL implementation that tracks renamed micro‑ops, determines operand readiness, and issues ready uops to execution pipelines. You will lead the design choices for distributed issue‑queues, wakeup/select logic, register‑file design, forwarding/result‑cache interfaces and dispatch steering, and will be accountable for the unit’s PPA, RTL quality and cross‑functional integration. This is a high‑visibility role with strong technical leadership and delivery expectations.
Responsibilities
Own the Issue/Scheduler unit delivery – translate microarchitecture specifications into an executable RTL plan, drive implementation to meet performance, power and area (PPA) targets and enforce RTL quality across the unit.
Drive PPA and power/energy optimization – lead efforts to lower power, quantify energy vs performance impacts and deliver measurable improvements without regressing IPC.
Champion verification & prototyping – collaborate with verification team on unit verification strategies, own prototyping and RTL closure activities, own documentation (including I/O specs) and ensure robust cross‑discipline validation with Verification, Performance and Physical design teams.
Lead and mentor – provide technical leadership and mentorship for engineers, lead technical reviews, and present design decisions and tradeoffs to senior stakeholders.
Required skills and experience
Extensive microarchitecture experience (typical 10+ years) in out‑of‑order CPUs, with direct ownership or design leadership for issue/wakeup/select/register file/scheduling logic and instruction dispatch subsystems.
Proven RTL ownership and delivery – track record translating uarch specs into RTL, collaborating with physical design team to meet PPA and schedule, and enforcing RTL quality standards.
Deep expertise in distributed issue‑queue architectures (multi‑queue configurations, write/read port tradeoffs, staging/shift‑once behavior and age/oldest selection).
Demonstrated PPA/energy optimization experience – ability to design and quantify architecture/RTL changes that trade performance, power and area effectively.
Verification and prototyping leadership – experience defining verification strategies, leading closure efforts and working closely with verification teams to validate complex CPU IP.
Excellent communication, stakeholder management and mentorship skills – able to lead technical reviews and represent the unit across the CPU program.
Proficiency in RTL and toolchain (Verilog/SystemVerilog/VHDL or equivalent), synthesis constraints, timing closure practices and modern verification methodologies.
Nice to have skills and experience
Track record of silicon/IP delivery (tapeout or equivalent) for CPU microarchitecture blocks.
Experience with performance‑modelling and microarchitecture simulation frameworks to predict IPC, wakeup/select latency and dispatch behavior.
Advanced degree (M.S./Ph.D.) in Computer/ Electrical Engineering or Computer Science, with specialization in computer architecture or microarchitecture research.
Prior experience leading a design unit or multiple teams and defining unit RTL quality standards.
In Return
Influence next‑generation CPU microarchitecture – you’ll shape core scheduling and Issue logic that directly determines performance for Arm CPUs.
High‑visibility, leadership role – a chance to lead a critical unit, mentor engineers, set RTL quality standards and make design decisions with program‑level impact.
Work at the frontier of PPA and energy optimization – apply and evaluate advanced techniques to reduce IQ energy while maintaining or improving IPC.
Cross‑functional collaboration and delivery – partner with front‑end, rename, verification, performance modelling and physical design teams to take concepts from specification through RTL, validation and delivery.
Salary Range : $241,100-$326,100 per year
Accommodations at Arm : If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com.
Hybrid Working at Arm : Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Details of what this means for each role will be shared upon application.
Equal Opportunities at Arm : Arm is an equal‑opportunity employer. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
#J-18808-Ljbffr
Principal Issue/Scheduler, Lead RTL Designer
role at
Arm .
About Arm
Arm is the industry’s leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address the performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, our technology is at the heart of a computing and connectivity revolution that continues to transform the way people live and businesses operate.
Job Overview
The Issue/Scheduler unit is central to an out‑of‑order CPU’s performance and PPA. As the Principal (G6) for this unit you will take ownership of the RTL implementation that tracks renamed micro‑ops, determines operand readiness, and issues ready uops to execution pipelines. You will lead the design choices for distributed issue‑queues, wakeup/select logic, register‑file design, forwarding/result‑cache interfaces and dispatch steering, and will be accountable for the unit’s PPA, RTL quality and cross‑functional integration. This is a high‑visibility role with strong technical leadership and delivery expectations.
Responsibilities
Own the Issue/Scheduler unit delivery – translate microarchitecture specifications into an executable RTL plan, drive implementation to meet performance, power and area (PPA) targets and enforce RTL quality across the unit.
Drive PPA and power/energy optimization – lead efforts to lower power, quantify energy vs performance impacts and deliver measurable improvements without regressing IPC.
Champion verification & prototyping – collaborate with verification team on unit verification strategies, own prototyping and RTL closure activities, own documentation (including I/O specs) and ensure robust cross‑discipline validation with Verification, Performance and Physical design teams.
Lead and mentor – provide technical leadership and mentorship for engineers, lead technical reviews, and present design decisions and tradeoffs to senior stakeholders.
Required skills and experience
Extensive microarchitecture experience (typical 10+ years) in out‑of‑order CPUs, with direct ownership or design leadership for issue/wakeup/select/register file/scheduling logic and instruction dispatch subsystems.
Proven RTL ownership and delivery – track record translating uarch specs into RTL, collaborating with physical design team to meet PPA and schedule, and enforcing RTL quality standards.
Deep expertise in distributed issue‑queue architectures (multi‑queue configurations, write/read port tradeoffs, staging/shift‑once behavior and age/oldest selection).
Demonstrated PPA/energy optimization experience – ability to design and quantify architecture/RTL changes that trade performance, power and area effectively.
Verification and prototyping leadership – experience defining verification strategies, leading closure efforts and working closely with verification teams to validate complex CPU IP.
Excellent communication, stakeholder management and mentorship skills – able to lead technical reviews and represent the unit across the CPU program.
Proficiency in RTL and toolchain (Verilog/SystemVerilog/VHDL or equivalent), synthesis constraints, timing closure practices and modern verification methodologies.
Nice to have skills and experience
Track record of silicon/IP delivery (tapeout or equivalent) for CPU microarchitecture blocks.
Experience with performance‑modelling and microarchitecture simulation frameworks to predict IPC, wakeup/select latency and dispatch behavior.
Advanced degree (M.S./Ph.D.) in Computer/ Electrical Engineering or Computer Science, with specialization in computer architecture or microarchitecture research.
Prior experience leading a design unit or multiple teams and defining unit RTL quality standards.
In Return
Influence next‑generation CPU microarchitecture – you’ll shape core scheduling and Issue logic that directly determines performance for Arm CPUs.
High‑visibility, leadership role – a chance to lead a critical unit, mentor engineers, set RTL quality standards and make design decisions with program‑level impact.
Work at the frontier of PPA and energy optimization – apply and evaluate advanced techniques to reduce IQ energy while maintaining or improving IPC.
Cross‑functional collaboration and delivery – partner with front‑end, rename, verification, performance modelling and physical design teams to take concepts from specification through RTL, validation and delivery.
Salary Range : $241,100-$326,100 per year
Accommodations at Arm : If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com.
Hybrid Working at Arm : Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Details of what this means for each role will be shared upon application.
Equal Opportunities at Arm : Arm is an equal‑opportunity employer. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
#J-18808-Ljbffr