Arm
Principal Issue/Scheduler, Lead RTL Designer
Join Arm in the role of
Principal Issue/Scheduler, Lead RTL Designer , a critical position responsible for ownership and delivery of the Issue/Scheduler unit in Arm's out‑of‑order CPU architecture. This high‑visibility role combines deep microarchitecture expertise with strong technical leadership and delivery expectations.
About Arm Arm is the world’s leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, Arm’s technology is at the heart of a computing and connectivity revolution that continues to transform how people live and businesses operate.
Job Overview The Issue/Scheduler unit is central to an out‑of‑order CPU’s performance and PPA. As the Principal (G6) for this unit you will take ownership of the RTL implementation that tracks renamed micro‑ops, determines operand readiness, and issues ready uops to execution pipelines. You will lead design choices for distributed issue‑queues, wakeup/select logic, register file design, forwarding/result‑cache interfaces and dispatch steering, and will be accountable for the unit’s PPA, RTL quality and cross‑functional integration.
Responsibilities
Own the Issue/Scheduler unit delivery – translate microarchitecture specifications into an executable RTL plan, drive implementation to meet performance, power and area (PPA) targets, and enforce RTL quality across the unit.
Drive PPA and power/energy optimization – lead efforts to lower power, quantify energy vs performance impacts and deliver measurable improvements without regressing IPC.
Champion verification & prototyping – collaborate with verification team on unit verification strategies, own prototyping and RTL closure activities, own documentation (including I/O specs) and ensure robust cross‑discipline validation with Verification, Performance and Physical design teams.
Lead and mentor – provide technical leadership and mentorship for engineers, lead technical reviews, and present design decisions and tradeoffs to senior stakeholders.
Required Skills and Experience
Extensive microarchitecture experience (10+ years) in out‑of‑order CPUs with direct ownership or design leadership for issue, wakeup, select, register‑file, scheduling logic and instruction dispatch subsystems.
Proven RTL ownership and delivery – track record translating uarch specs into RTL, collaborating with physical design team to meet PPA and schedule, and enforcing RTL quality standards.
Deep expertise in distributed issue‑queue architectures, including multi‑queue configurations, write/read port tradeoffs, staging/shift‑once behavior and age/oldest selection.
Demonstrated PPA/energy optimization experience – ability to design and quantify architecture/RTL changes that trade performance, power and area effectively.
Verification and prototyping leadership – experience defining verification strategies, leading closure efforts and working closely with verification teams to validate complex CPU IP.
Excellent communication, stakeholder management and mentorship skills – able to lead technical reviews and represent the unit across the CPU program.
Proficiency in RTL and toolchain (Verilog/SystemVerilog/VHDL or equivalent), synthesis constraints, timing closure practices and modern verification methodologies.
Nice to Have Skills and Experience
Track record of silicon/IP delivery (tapeout or equivalent) for CPU microarchitecture blocks.
Experience with performance‑modelling and microarchitecture simulation frameworks to predict IPC, wakeup/select latency and dispatch behaviour.
Advanced degree (M.S./Ph.D.) in Computer/ Electrical Engineering or Computer Science, with specialization in computer architecture or microarchitecture research.
Prior experience leading a design unit or multiple teams and defining unit RTL quality standards.
In Return
Influence next‑generation CPU microarchitecture – you’ll shape core scheduling and issue logic that directly determines performance for Arm CPUs.
High‑visibility, leadership role – a chance to lead a critical unit, mentor engineers, set RTL quality standards and make design decisions with program‑level impact.
Work at the frontier of PPA and energy optimization – apply and evaluate advanced techniques to reduce IQ energy while maintaining or improving IPC.
Cross‑functional collaboration and delivery – partner with front‑end, rename, verification, performance modelling and physical design teams to take concepts from spec through RTL, validation and delivery.
10x Mindset Our 10x mindset guides how we engineer, collaborate, and grow.
Understand what it means and how to reflect 10x in your work .
Salary Range $241,100–$326,100 per year
Accommodations at Arm Arm is committed to providing an inclusive, equitable and respectful workplace. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. All accommodation or adjustment requests will be treated with confidentiality and disclosed only as needed to provide the accommodation.
Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application.
Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Management and Manufacturing
Industries Semiconductor Manufacturing, Software Development, and Computer Hardware Manufacturing
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Principal Issue/Scheduler, Lead RTL Designer , a critical position responsible for ownership and delivery of the Issue/Scheduler unit in Arm's out‑of‑order CPU architecture. This high‑visibility role combines deep microarchitecture expertise with strong technical leadership and delivery expectations.
About Arm Arm is the world’s leading supplier of microprocessor technology, offering the widest range of microprocessor cores to address performance, power, and cost requirements for almost all application markets. With a vibrant ecosystem of over 1,000 partners and more than 150 billion processors shipped, Arm’s technology is at the heart of a computing and connectivity revolution that continues to transform how people live and businesses operate.
Job Overview The Issue/Scheduler unit is central to an out‑of‑order CPU’s performance and PPA. As the Principal (G6) for this unit you will take ownership of the RTL implementation that tracks renamed micro‑ops, determines operand readiness, and issues ready uops to execution pipelines. You will lead design choices for distributed issue‑queues, wakeup/select logic, register file design, forwarding/result‑cache interfaces and dispatch steering, and will be accountable for the unit’s PPA, RTL quality and cross‑functional integration.
Responsibilities
Own the Issue/Scheduler unit delivery – translate microarchitecture specifications into an executable RTL plan, drive implementation to meet performance, power and area (PPA) targets, and enforce RTL quality across the unit.
Drive PPA and power/energy optimization – lead efforts to lower power, quantify energy vs performance impacts and deliver measurable improvements without regressing IPC.
Champion verification & prototyping – collaborate with verification team on unit verification strategies, own prototyping and RTL closure activities, own documentation (including I/O specs) and ensure robust cross‑discipline validation with Verification, Performance and Physical design teams.
Lead and mentor – provide technical leadership and mentorship for engineers, lead technical reviews, and present design decisions and tradeoffs to senior stakeholders.
Required Skills and Experience
Extensive microarchitecture experience (10+ years) in out‑of‑order CPUs with direct ownership or design leadership for issue, wakeup, select, register‑file, scheduling logic and instruction dispatch subsystems.
Proven RTL ownership and delivery – track record translating uarch specs into RTL, collaborating with physical design team to meet PPA and schedule, and enforcing RTL quality standards.
Deep expertise in distributed issue‑queue architectures, including multi‑queue configurations, write/read port tradeoffs, staging/shift‑once behavior and age/oldest selection.
Demonstrated PPA/energy optimization experience – ability to design and quantify architecture/RTL changes that trade performance, power and area effectively.
Verification and prototyping leadership – experience defining verification strategies, leading closure efforts and working closely with verification teams to validate complex CPU IP.
Excellent communication, stakeholder management and mentorship skills – able to lead technical reviews and represent the unit across the CPU program.
Proficiency in RTL and toolchain (Verilog/SystemVerilog/VHDL or equivalent), synthesis constraints, timing closure practices and modern verification methodologies.
Nice to Have Skills and Experience
Track record of silicon/IP delivery (tapeout or equivalent) for CPU microarchitecture blocks.
Experience with performance‑modelling and microarchitecture simulation frameworks to predict IPC, wakeup/select latency and dispatch behaviour.
Advanced degree (M.S./Ph.D.) in Computer/ Electrical Engineering or Computer Science, with specialization in computer architecture or microarchitecture research.
Prior experience leading a design unit or multiple teams and defining unit RTL quality standards.
In Return
Influence next‑generation CPU microarchitecture – you’ll shape core scheduling and issue logic that directly determines performance for Arm CPUs.
High‑visibility, leadership role – a chance to lead a critical unit, mentor engineers, set RTL quality standards and make design decisions with program‑level impact.
Work at the frontier of PPA and energy optimization – apply and evaluate advanced techniques to reduce IQ energy while maintaining or improving IPC.
Cross‑functional collaboration and delivery – partner with front‑end, rename, verification, performance modelling and physical design teams to take concepts from spec through RTL, validation and delivery.
10x Mindset Our 10x mindset guides how we engineer, collaborate, and grow.
Understand what it means and how to reflect 10x in your work .
Salary Range $241,100–$326,100 per year
Accommodations at Arm Arm is committed to providing an inclusive, equitable and respectful workplace. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. All accommodation or adjustment requests will be treated with confidentiality and disclosed only as needed to provide the accommodation.
Hybrid Working at Arm Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application.
Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Management and Manufacturing
Industries Semiconductor Manufacturing, Software Development, and Computer Hardware Manufacturing
#J-18808-Ljbffr