Senior DFT Design Architect for SoC/ASIC

A leading technology firm is seeking an experienced SoC/ASIC Digital Design Engineer in San Jose, California. The candidate will focus on Design for Test (DFT), requiring experience in scan chain insertion, compression scan technologies, and Automatic Test Pattern Generation (ATPG). Ideal candidates will demonstrate strong problem-solving skills and collaboration with cross-functional teams. This role encourages independent task completion and values US citizenship. A calculated method and discipline in addressing challenges are key for success in this fast-paced environment. #J-18808-Ljbffr