pSemi, A Murata Company
Technical Director, Digital Design and Verification
pSemi, A Murata Company, San Diego, California, United States, 92189
Technical Director, Digital Design and Verification
Join to apply for the
Technical Director, Digital Design and Verification
role at
pSemi, A Murata Company .
pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.
Job Summary The Technical Director of Digital Design and Verification supervises and directs teams in San Diego, CA and Austin, TX, as well as the pSemi India Design Center (IDC) in Chennai, India. The Technical Director is expected to lead, hire, train, and mentor engineers to develop industry-leading solutions. As the technical leader, this person manages and guides their team, drives digital design, develops processes and methodologies, including defining verification methodology, and tracks deliverables to ensure timely and high-quality execution. The Technical Director works with cross‑functional teams—Marketing, Product, and Test Engineering—to support pSemi’s advanced products and IP from definition through release to end‑of‑life.
Roles & Responsibilities
Manage and mentor digital design and verification teams across multiple sites
Drive hiring, training, and career development initiatives
Oversee project planning, resource allocation, and deliverable tracking
Architect, design, and verify digital logic to meet critical power, performance, and area targets
Contribute to the design team’s efficiency, productivity, and quality through flow and methodology improvements
Prepare and hold architecture, design, and verification reviews with technical staff through the project life cycle
Support Front‑end & Mid‑end tasks such as synthesis, timing closure, DFT, ATPG, etc.
Support test vector generation and silicon validation
Support digital characterization programs and data analysis
Support AMS verification
Work with interdisciplinary teams to identify automation and tool requirements
Ensure smooth transition from design to mass production
Minimum Qualifications (Experience And Skills)
15+ years of experience or equivalent in digital design and verification
5+ years of experience managing individuals and teams
Excellent communication, management, and coaching skills; able to simplify complex ideas and mentor team members to grow and achieve excellent results
Demonstrated project management skill to coordinate activities across multiple designs simultaneously
Ability to work in a fast‑paced, multi‑tasking environment
Demonstrated experience in ASIC systems and circuit analysis, digital architectures, design & front‑end support, verification/validation, mid/back‑end coordination, test, product development, and mass production product releases
Key technical skillsets:
Fundamental knowledge of digital circuits, transistor‑level design, systems, and architectures
Strong knowledge of digital methodologies and flows
In‑depth knowledge of RTL/Verilog, and familiarity with mid/back‑end digital design
Expertise in front‑end digital including timing, synthesis
Expertise designing digital circuits, state‑machines, serial interfaces, and integrating IP such as SRAM, OTP
Familiarity with interface specifications such as MIPI RFEE, SPI, I2C, I3C, etc.
Experience working in sub‑micron technologies, low‑power domain
Strong knowledge of clock‑domain crossing, power‑domain methodologies and designs, low‑power designs
Fundamental knowledge of high‑level programming languages – C++, C#, Perl, Python, Tcl, Makefile
Deep experience with Cadence and Synopsys tool suites
Familiarity with pre‑silicon verification and post‑silicon validation tools and methodologies, e.g., SystemVerilog, UVM, and Lab‑equipment
Familiarity with DFT and scan insertion
Preferred Qualifications
Knowledge of communication systems and DSP architectures in signal‑processing ASICs, as well as mixed‑signal design, including delta‑sigma modulators, interpolation/decimation filters, and fixed‑point arithmetic
Understanding of discrete‑time, z‑domain, digital signal processing, digital filter design (FIR, IIR)
Ability to model control‑loop feedback and signal‑processing algorithms using tools such as MATLAB & Simulink
Experience with Standard Cell Library development and characterization
Familiarity with low‑power design techniques including UPF/CPF
Experience developing the digital logic needed for calibration, control, data processing, and enablement for the mixed‑signal IP and ASICs; performing integration of mixed‑signal IP
Experience with FPGA to validate digital RTL and gates is desired
Behavioral modeling of RF and AMS circuits for ASIC/module level verification
Strong understanding of design verification techniques such as UVM and formal verification methods
Experience in IP development and integration
Understanding of semiconductor consumer‑product life cycle
Experience working with global design and cross‑functional teams
Education Requirements
Minimum of Master’s Degree in Electrical Engineering/Computer Engineering or equivalent experience; PhD preferred
Work Environment This role operates in a professional office environment. This role routinely uses standard office equipment.
Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception, and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.
Salary USD 212,186.16 - 291,755.96 per year
EEO Statement pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally‑protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.
Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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Technical Director, Digital Design and Verification
role at
pSemi, A Murata Company .
pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.
Job Summary The Technical Director of Digital Design and Verification supervises and directs teams in San Diego, CA and Austin, TX, as well as the pSemi India Design Center (IDC) in Chennai, India. The Technical Director is expected to lead, hire, train, and mentor engineers to develop industry-leading solutions. As the technical leader, this person manages and guides their team, drives digital design, develops processes and methodologies, including defining verification methodology, and tracks deliverables to ensure timely and high-quality execution. The Technical Director works with cross‑functional teams—Marketing, Product, and Test Engineering—to support pSemi’s advanced products and IP from definition through release to end‑of‑life.
Roles & Responsibilities
Manage and mentor digital design and verification teams across multiple sites
Drive hiring, training, and career development initiatives
Oversee project planning, resource allocation, and deliverable tracking
Architect, design, and verify digital logic to meet critical power, performance, and area targets
Contribute to the design team’s efficiency, productivity, and quality through flow and methodology improvements
Prepare and hold architecture, design, and verification reviews with technical staff through the project life cycle
Support Front‑end & Mid‑end tasks such as synthesis, timing closure, DFT, ATPG, etc.
Support test vector generation and silicon validation
Support digital characterization programs and data analysis
Support AMS verification
Work with interdisciplinary teams to identify automation and tool requirements
Ensure smooth transition from design to mass production
Minimum Qualifications (Experience And Skills)
15+ years of experience or equivalent in digital design and verification
5+ years of experience managing individuals and teams
Excellent communication, management, and coaching skills; able to simplify complex ideas and mentor team members to grow and achieve excellent results
Demonstrated project management skill to coordinate activities across multiple designs simultaneously
Ability to work in a fast‑paced, multi‑tasking environment
Demonstrated experience in ASIC systems and circuit analysis, digital architectures, design & front‑end support, verification/validation, mid/back‑end coordination, test, product development, and mass production product releases
Key technical skillsets:
Fundamental knowledge of digital circuits, transistor‑level design, systems, and architectures
Strong knowledge of digital methodologies and flows
In‑depth knowledge of RTL/Verilog, and familiarity with mid/back‑end digital design
Expertise in front‑end digital including timing, synthesis
Expertise designing digital circuits, state‑machines, serial interfaces, and integrating IP such as SRAM, OTP
Familiarity with interface specifications such as MIPI RFEE, SPI, I2C, I3C, etc.
Experience working in sub‑micron technologies, low‑power domain
Strong knowledge of clock‑domain crossing, power‑domain methodologies and designs, low‑power designs
Fundamental knowledge of high‑level programming languages – C++, C#, Perl, Python, Tcl, Makefile
Deep experience with Cadence and Synopsys tool suites
Familiarity with pre‑silicon verification and post‑silicon validation tools and methodologies, e.g., SystemVerilog, UVM, and Lab‑equipment
Familiarity with DFT and scan insertion
Preferred Qualifications
Knowledge of communication systems and DSP architectures in signal‑processing ASICs, as well as mixed‑signal design, including delta‑sigma modulators, interpolation/decimation filters, and fixed‑point arithmetic
Understanding of discrete‑time, z‑domain, digital signal processing, digital filter design (FIR, IIR)
Ability to model control‑loop feedback and signal‑processing algorithms using tools such as MATLAB & Simulink
Experience with Standard Cell Library development and characterization
Familiarity with low‑power design techniques including UPF/CPF
Experience developing the digital logic needed for calibration, control, data processing, and enablement for the mixed‑signal IP and ASICs; performing integration of mixed‑signal IP
Experience with FPGA to validate digital RTL and gates is desired
Behavioral modeling of RF and AMS circuits for ASIC/module level verification
Strong understanding of design verification techniques such as UVM and formal verification methods
Experience in IP development and integration
Understanding of semiconductor consumer‑product life cycle
Experience working with global design and cross‑functional teams
Education Requirements
Minimum of Master’s Degree in Electrical Engineering/Computer Engineering or equivalent experience; PhD preferred
Work Environment This role operates in a professional office environment. This role routinely uses standard office equipment.
Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception, and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.
Salary USD 212,186.16 - 291,755.96 per year
EEO Statement pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally‑protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.
Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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