Senior IP Verification Engineer - Multimedia & SoC

A leading technology company in Santa Clara is looking for a Senior Verification Engineer to be part of their multi-media IP team. The role includes collaborating with ASIC design engineers, verifying IPs using System Verilog, and developing verification architectures. Candidates should have a BS/MS in Electrical or Computer Engineering and over 5 years of experience in design verification. This position offers competitive salaries with a base salary range of $136,000 - $212,750 for Level 3 and $168,000 - $264,500 for Level 4, along with equity and benefits. #J-18808-Ljbffr