Senior Analog Layout Engineer (High Speed / Precision Analog)
UST, Santa Clara, California, us, 95053
Role description
Senior Analog Layout Engineer (High Speed / Precision Analog) Technical Lead I - VLSI You Are:
We are seeking an experienced Senior Analog Layout Engineer with strong expertise in high speed and precision analog layout design for deep sub micron FinFET technologies. The opportunity:
Perform custom analog layout design for high speed and precision analog circuits in advanced FinFET process technologies Design and implement layout for high speed SerDes blocks, including:
Equalizers PLLs Phase Interpolators CDRs
Develop layout for precision analog blocks such as:
ADCs DACs
Execute floorplanning and support design sign off closure, including handling:
Multiple power rails ESD requirements
Integrate digital hard IPs into complex analog/mixed signal designs Perform DRC/LVS debugging and resolve layout related issues efficiently Utilize and develop SKILL scripts to improve layout productivity and automation Work closely with circuit designers, verification, and process teams to ensure layout meets performance, reliability, and manufacturability requirements What you need:
BS or MS in Electrical Engineering 8+ years of hands-on experience in high speed and precision analog layout design Strong experience in deep sub-micron FinFET process technologies Proficiency with standard industry layout and verification tools, such as:
Cadence Synopsys Calibre
Proven experience in custom layout design for high speed and precision analog circuits Solid understanding of DRC/LVS verification flows Hands-on experience with SKILL coding Preferred / Plus Skills Experience in complex SoC or mixed signal integration environments Strong understanding of signal integrity, matching, and parasitic effects Experience working on high performance, low power designs Good communication skills and ability to collaborate across global teams Experience Level 8+ years of relevant industry experience Compensation & Benefits
Role Location: California Compensation Range: $87,000-$131,000 Benefits
Full-time employees accrue vacation, sick leave, holidays, and participate in benefits described (401(k) with employer matching, medical/dental/vision, life insurance, disability, HSA/FSAs where applicable). Benefits vary by location and employee type. Equal Employment Opportunity
UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and fair chance ordinances.
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Senior Analog Layout Engineer (High Speed / Precision Analog) Technical Lead I - VLSI You Are:
We are seeking an experienced Senior Analog Layout Engineer with strong expertise in high speed and precision analog layout design for deep sub micron FinFET technologies. The opportunity:
Perform custom analog layout design for high speed and precision analog circuits in advanced FinFET process technologies Design and implement layout for high speed SerDes blocks, including:
Equalizers PLLs Phase Interpolators CDRs
Develop layout for precision analog blocks such as:
ADCs DACs
Execute floorplanning and support design sign off closure, including handling:
Multiple power rails ESD requirements
Integrate digital hard IPs into complex analog/mixed signal designs Perform DRC/LVS debugging and resolve layout related issues efficiently Utilize and develop SKILL scripts to improve layout productivity and automation Work closely with circuit designers, verification, and process teams to ensure layout meets performance, reliability, and manufacturability requirements What you need:
BS or MS in Electrical Engineering 8+ years of hands-on experience in high speed and precision analog layout design Strong experience in deep sub-micron FinFET process technologies Proficiency with standard industry layout and verification tools, such as:
Cadence Synopsys Calibre
Proven experience in custom layout design for high speed and precision analog circuits Solid understanding of DRC/LVS verification flows Hands-on experience with SKILL coding Preferred / Plus Skills Experience in complex SoC or mixed signal integration environments Strong understanding of signal integrity, matching, and parasitic effects Experience working on high performance, low power designs Good communication skills and ability to collaborate across global teams Experience Level 8+ years of relevant industry experience Compensation & Benefits
Role Location: California Compensation Range: $87,000-$131,000 Benefits
Full-time employees accrue vacation, sick leave, holidays, and participate in benefits described (401(k) with employer matching, medical/dental/vision, life insurance, disability, HSA/FSAs where applicable). Benefits vary by location and employee type. Equal Employment Opportunity
UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and fair chance ordinances.
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